Elektronika 2009-11.pdf - Instytut Systemów Elektronicznych
Elektronika 2009-11.pdf - Instytut Systemów Elektronicznych
Elektronika 2009-11.pdf - Instytut Systemów Elektronicznych
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Example of concurrent resource<br />
allocation and task scheduling<br />
Let us discuss a simple example for management of multiprocessors<br />
system with fault tolerant where assuming that<br />
tasks (with applications requirements) of the system are given<br />
by the tasks graph. The digraph presented in Fig. 4 defines<br />
the precedence constraints of tasks of the modeled system.<br />
Fig. 4. Task digraph Rys. 4. Graf zadań<br />
The optimality criterion is the minimum of the task processing<br />
time, i.e. a minimum of the task schedule length. An<br />
additional criterion is cost, related to the number of used resources.<br />
We shall define constraints of the resources available.<br />
Compilation of all operations [6] of the system, the<br />
characteristics of available resources and database (with resource<br />
allocations in the past) give us the times of task processing<br />
(we assume conventional time units).<br />
We assume the following times of individual tasks for a<br />
standard processor: t 0 = 3, t 1 = 2, t 2 = 2, t 3 = 1, t 4 = 3, t 5 = 3,<br />
t 6 = 4, t 7 = 3, t 8 = 1, t 9 = 1. Let us assume that the cost of one<br />
executive module is:<br />
C = C P + i • C M (1)<br />
where: C P - processor cost, C M - memory module cost,<br />
i - number of memory modules.<br />
The requirements for realizing all operations of the system<br />
shall be specified as follows:<br />
• the acceptable deadline for performing all tasks without any<br />
delays is 13 time units;<br />
• it is necessary to perform task T 6 indivisibly in time;<br />
• it is necessary to provide a deadline for task T 6 equal<br />
9 time units;<br />
• the desirable deadline for performing all tasks without any<br />
delays is at most 10 time units.<br />
The cost of the system should be as low as possible, and<br />
the structure conformable to the fault tolerance system model<br />
with two-processor testing tasks. We shall denote processor<br />
testing tasks by T gh , if processor P g is testing processor P h .<br />
The first step of the planning has to determine the number<br />
of parallel processors needed for the execution of all requirements<br />
and constraints. The structure of four parallel<br />
processors shall be assumed. This structure of a fault tolerance<br />
the system satisfying the requirement “1.” is shown in<br />
Fig. 5 (variant a).<br />
Fig. 5. Structures of fault tolerance multiprocessor system<br />
Rys. 5. Struktury wieloprocesorowe z tolerancją uszkodzeń<br />
The optimum tasks schedule for such architecture is presented<br />
in Table 1. Taking into account the requirement “2.”,<br />
a correction is done to the task schedule. The system structure<br />
and costs remain unchanged.<br />
The next requirement “3.” is reflected in a corrected<br />
schedule presented in Table 1. Please notice that the system<br />
architecture and costs remain unchanged. Only tasks schedule<br />
is modified.<br />
In order to carry out the requirement “4.”, a change of the<br />
system structure is necessary. Two variants of the structure<br />
shall be proposed. The first structure consists of five identical<br />
parallel processors, with two-processor testing tasks Fig. 2 -<br />
variant b). Task schedule in such structure is depicted in<br />
Table 2 (variant b). In the second variant, a specialized module<br />
(ASIC - if is available) is applied that can perform the<br />
Tabl. 1. Schedule of task in a four-processors (structure: variant a) satisfying<br />
the requirement “1.”= (1) and “1.”+”2.”+”3.” = (3) (X - idle time)<br />
Tab. 1. Uszeregowanie zadań na 4 procesorach (struktura: wariant a)<br />
zgodnie z wymaganiami ”1.” = (1) i “1.”+”2.”+”3.” = (3) (X - czas przestoju<br />
procesora)<br />
time P1 (1) P2 (1) P3 (1) P4 (1) P1 (3) P2 (3) P3 (3) P4 (3)<br />
1 T12 T12 T0 X T12 T12 T0 X<br />
2 T0 T23 T23 X T0 T23 T23 X<br />
3 T0 X T34 T34 T0 X T34 T34<br />
4 T13 T1 T13 T2 T13 T1 T13 T2<br />
5 T1 T24 T2 T24 T1 T24 T2 T24<br />
6 T31 T4 T31 T3 T31 T6 T31 T3<br />
7 T14 T4 T5 T14 T14 T6 T5 T14<br />
8 T21 T21 T4 T6 T21 T21 T4 T6<br />
9 T7 T32 T32 T6 T7 T32 T32 T6<br />
10 T41 T6 T5 T41 T41 T4 T5 T41<br />
11 T7 T42 T5 T42 T4 T42 T5 T42<br />
12 T6 T8 T43 T43 T6 T8 T43 T43<br />
13 T12 T12 T7 T9 T12 T12 T7 T9<br />
Tabl. 2. Schedule of tasks in a five-processors (structure: variant b)<br />
and in a three-processors with specialized ASIC processor (structure:<br />
variant c) satisfying the requirements “1.”+”2.”+”3.”+”4.” (X - idle time)<br />
Tab. 2. Uszeregowanie zadań na 5 procesorach (struktura: wariant b)<br />
i na 3 procesorach z procesorem specjalizowanym ASIC (struktura<br />
wariant c) zgodnie z wymaganiami “1.”+”2.”+”3.” +”4.” (X - czas przestoju<br />
procesora)<br />
time P1 (b) P2 (b) P3 (b) P4 (b) P5 (b) P1 (c) P2 (c) P3 (c) ASIC (c)<br />
1 T12 T12 X T0 X T12 T12 X T0<br />
2 X T23 T23 T0 X T2 T23 T23 X<br />
3 X X T34 T34 T0 T13 T2 T13 X<br />
4 T1 T2 T6 T45 T45 T21 T21 T6 T4<br />
5 T13 T2 T13 T1 T6 T1 T32 T32 T6<br />
6 T3 T24 T5 T24 T6 T31 T1 T31 X<br />
7 T4 T5 T35 T6 T35 T12 T12 T3 T5<br />
8 T14 T5 T4 T14 T7 T8 T23 T23 T7<br />
9 T9 T25 T4 T7 T25 T13 T13 T9 X<br />
10 T15 T8 T9 T7 T15 X X X X<br />
11 T21 T21 X X X X X X X<br />
12 X T32 T32 X X X X X X<br />
13 X X T43 T43 X X X X X<br />
40 ELEKTRONIKA 11/<strong>2009</strong>