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CHAPTER 10<br />

Frequency Compensation<br />

Analog IC Analysis and Design 10-1<br />

Chih-Cheng Hsieh


Outline<br />

1. General Consideration<br />

2. Phase Margin<br />

3. Frequency Compensation<br />

4. Compensation of Two-Stage Op Amps<br />

5. Other Compensation Techniques<br />

Analog IC Analysis and Design 10-2<br />

Chih-Cheng Hsieh


General Consideration<br />

Y<br />

X<br />

( s)<br />

=<br />

H ( s)<br />

1+ βH<br />

( s)<br />

• Consider the negative feedback system, where β is assumed constant<br />

• If βH<br />

( s = jω1 ) = −1<br />

, the gain goes to infinity, and the circuit can amplify its own<br />

noise until it eventually begins to oscillate.<br />

• Barkhausen’s Criteria : The circuit may oscillate at frequency<br />

o<br />

( jω<br />

) = ∠βH<br />

( jω<br />

) =<br />

βH 180<br />

1<br />

1<br />

1<br />

−<br />

• The total phase shift around the loop at ω 1 is 360 o . (180 o from negative feedback)<br />

• The feedback signal add in phase to the original noise to allow oscillation buildup.<br />

ω 1<br />

if<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

3


Bode Plot for Stability Analysis<br />

• Assume that β is less than or equal to unity and does not depend on the<br />

frequency.<br />

• The worst case stability corresponds to β = 1.<br />

• We often analyze the magnitude and phase plots for βH = H .<br />

Unstable<br />

Stable<br />

• In a stable system<br />

Gain<br />

20log βH<br />

Margin = −20log<br />

βH<br />

o<br />

( jω<br />

o ) < 0 ∠βH<br />

( jωunity<br />

) > −180<br />

180<br />

o<br />

( jω<br />

o ) Phase Margin = 180 + ∠βH<br />

( jω<br />

)<br />

180<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

4<br />

unity


Time Response vs. the Position of Poles<br />

• Expressing each pole frequency as<br />

s<br />

p<br />

=<br />

jω + σ<br />

p<br />

p<br />

• The impulse response of the system<br />

includes a term<br />

exp(<br />

jω + σ )t<br />

p<br />

p<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

5


Stability and Pole Location<br />

http://en.wikipedia.org/wiki/Laplace_transform<br />

Consider an amplifier with a complex-conjugate pole pair : s = σ0 ± jωn<br />

σ0 0<br />

( ) t [ j ωn<br />

t − j ωn<br />

t σ<br />

] 2 t cos( )<br />

vt = e e + e = e ω t<br />

A sinusoidal signal with an envelope<br />

n<br />

0<br />

e σ t<br />

Stable system<br />

Left-plane pole<br />

σ<br />

0<br />

< 0<br />

: Oscillation decays exponentially to zero.<br />

Analog IC Analysis and Design 10-6<br />

Chih-Cheng Hsieh


Stability and Pole Location<br />

Right-plane pole<br />

σ<br />

0<br />

> 0<br />

: Oscillation grows exponentially to nonlinear.<br />

Unstable system<br />

jw axis pole<br />

σ<br />

0<br />

= 0<br />

: Oscillation sustained.<br />

Oscillation system<br />

The existence of any righ-half-plane poles results in instability<br />

Analog IC Analysis and Design 10-7<br />

Chih-Cheng Hsieh


Bode Plots of Loop Gain<br />

• Consider an one pole amplifier<br />

A0<br />

H()<br />

s = ⎛<br />

1 s ⎞<br />

⎜ +<br />

ω ⎟<br />

⎝ 0 ⎠<br />

A0<br />

Y 1+<br />

β A<br />

() s =<br />

X<br />

1+<br />

s<br />

ω<br />

0<br />

( 1+<br />

βA<br />

)<br />

0 0<br />

• A single pole cannot contribute a phase shift greater than 90 o , and the system is<br />

unconditionally stable for all non-negative values of β.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

8


Two-pole Systems<br />

• Consider a two-pole system<br />

H()<br />

s<br />

0<br />

= ⎛<br />

1 s ⎞⎛<br />

1 s ⎞<br />

⎜ +<br />

ω ⎟⎜ +<br />

P1 ω ⎟<br />

⎝ ⎠⎝ P2⎠<br />

Y<br />

A0<br />

() s =<br />

X ⎛ s ⎞⎛ s ⎞<br />

1+ 1+ + β A<br />

⎜<br />

⎟⎜ ω ⎟⎜ ω ⎟<br />

A<br />

⎝ p1⎠⎝ p2<br />

⎠<br />

0<br />

• Maximum phase shift = 180 o<br />

• As the feedback becomes weaker, the gain crossover point moves toward the<br />

origin.<br />

• The stability is obtained at the cost of weaker feedback.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

9


Multipole Systems<br />

• Consider a 3-pole system<br />

• Maximum phase shift = 270 o<br />

• The phase begins to change at 0.1 of pole<br />

frequency whereas the magnitude begins to<br />

drop only near the pole frequency.<br />

• Additional poles(and zeros) impact the phase to<br />

a much greater extent than magnitude.<br />

• The stability is obtained at the cost of weaker<br />

feedback.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

10


Outline<br />

1. General Consideration<br />

2. Phase Margin<br />

3. Frequency Compensation<br />

4. Compensation of Two-Stage Op Amps<br />

5. Other Compensation Techniques<br />

Analog IC Analysis and Design 10-11<br />

Chih-Cheng Hsieh


Phase Margin<br />

• If<br />

o<br />

o<br />

( u ) 175 , ( 1) 1 exp( 175 )<br />

∠ βH jω =− βH jω<br />

= × −j<br />

1 exp 175<br />

Y H β<br />

1 −0. 9962 − j 0.<br />

0872<br />

( jω1<br />

) = = = ⋅<br />

X 1+ βH j ω 1+ exp − 175 β 0. 0038 − j 0.<br />

0872<br />

( jω1<br />

)<br />

( )<br />

1<br />

o<br />

( − j )<br />

o<br />

( j )<br />

Y<br />

X<br />

( jω<br />

)<br />

1 1<br />

⋅<br />

β 0.0872<br />

1<br />

= ≈<br />

11.5<br />

β<br />

Y<br />

1<br />

• Since at low frequencies, ≈<br />

X β , the closed-loop frequency response<br />

exhibits a sharp peak in the vicinity of ω = ω 1<br />

• The closed loop system is near oscillation and its step response exhibits a very<br />

underdamped behavior.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

12


Closed-Loop Freq. and Time Response<br />

‣ For a small phase margin<br />

log βH<br />

( ω)<br />

‣ For a large phase margin<br />

log βH<br />

( ω)<br />

∠βH ( ω)<br />

∠βH ( ω)<br />

• The greater the phase margin, the more stable the feedback system.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

13


CL Freq. Response with 45 o PM<br />

• For PM = 45 o ,<br />

∠βH<br />

o<br />

( ω ) = − βH<br />

( ω ) 1<br />

1<br />

135<br />

1<br />

=<br />

Y<br />

X<br />

H<br />

1<br />

=<br />

1+<br />

1×<br />

exp( − j135<br />

( jω<br />

) H ( jω<br />

)<br />

o<br />

)<br />

1<br />

=<br />

0.29 − 0.71j<br />

Y<br />

X<br />

=<br />

1<br />

⋅<br />

β<br />

1<br />

0.29 − 0.71j<br />

1.3<br />

≈<br />

β<br />

– The feedback system suffers from a 30% peak at ω = ω 1<br />

• For PM = 60 o , the peaking is negligible<br />

1<br />

=<br />

β<br />

• The concept of phase margin is well-suited to the<br />

design of circuits that process small signals, not large<br />

signals.<br />

Y<br />

X<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

14


Outline<br />

1. General Consideration<br />

2. Phase Margin<br />

3. Frequency Compensation<br />

4. Compensation of Two-Stage Op Amps<br />

5. Other Compensation Techniques<br />

Analog IC Analysis and Design 10-15<br />

Chih-Cheng Hsieh


Frequency Compensation<br />

• Frequency compensation : their open loop transfer function must be modified such that<br />

the closed-loop circuit is stable and the time response is well behaved.<br />

• Frequency compensation can be achieved by<br />

– Minimizing the overall phase shift, thus pushing the phase crossover out.<br />

– Dropping the gain, thereby pushing the gain crossover in.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

16


Single-Ended Telescopic OP Amp.<br />

• Frequency compensation : their open loop transfer function must be modified<br />

such that the closed-loop circuit is stable and the time response is well behaved.<br />

• Path 1 : a high-frequency pole at the source of M 3 , a mirror pole at node A,<br />

another high-frequency pole at the source of M 7 , and a pole at the output.<br />

• Path2 : a high-frequency pole at the source of M 4 , and a pole at the output.<br />

• Dominant pole (d.p.) : ω p,out usually sets the open loop 3-dB bandwidth.<br />

• Non-dominant pole : the closet pole to the origin after the d.p. is at node A.<br />

C = C + C + C + C + C + C<br />

A<br />

GS 5 GS 6 DB5<br />

2<br />

GD6<br />

DB3<br />

GD3<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

17


Bode Plots of Telescopic OP Amp<br />

• The mirror pole typically limits the phase margin.<br />

• The circuit contains a zero at 2ω p,A . (ignore it now for simplicity)<br />

• Force the loop gain to drop the gain crossover point moves toward the origin.<br />

• The dominant pole can be pushed to a lower freq. by increasing the load cap.<br />

• The unity-gain bandwidth of the compensated op amp is equal to the frequency<br />

of the 1 st non-dominant pole.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

18


Bode Plots of Loop Gain for Higher R o<br />

• Translating the dominant pole toward the origin for 45 o phase margin, the unity<br />

gain frequency is equal to the frequency of the first non-dominant pole.<br />

• Increasing R out does not compensate the op amp.<br />

• To achieve a wideband in a feedback system, the 1 st nondominant pole must be<br />

as far as possible The mirror pole is undesirable.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

19


Fully Differential Telescopic Op Amp<br />

• This topology avoids the mirror pole, thereby<br />

exhibiting stable behavior for a greater bandwidth.<br />

• One dominant pole at the output node and only<br />

one nondominant pole arising from node X (or Y).<br />

• Capacitance at node N, C N = C GS5 + C SB5 + C GD7 +<br />

C DB7 , shunts the output resistance of M 7 at high<br />

frequencies, thereby dropping the output<br />

impedance of the cascode.<br />

• The pole in the PMOS cascode is merged with the<br />

output pole, thus creating no additional pole.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

20<br />

Z<br />

out<br />

( )<br />

−<br />

( )<br />

Z = 1 + g r Z + r ,<br />

out m5 O5 N O5<br />

Z = r || C s ,<br />

N O7<br />

N<br />

1<br />

( 1 )<br />

Z ≈ + g r<br />

out m5 O5<br />

1<br />

||<br />

sC<br />

L<br />

=<br />

rO<br />

7<br />

1+<br />

sr C<br />

O7<br />

( 1+<br />

gm5rO<br />

5<br />

) rO<br />

7<br />

[( 1+<br />

g r ) r C + r C ] s + 1<br />

m5<br />

O5<br />

O7<br />

N<br />

L<br />

O7<br />

N


Outline<br />

1. General Consideration<br />

2. Phase Margin<br />

3. Frequency Compensation<br />

4. Compensation of Two-Stage Op Amps<br />

5. Other Compensation Techniques<br />

Analog IC Analysis and Design 10-21<br />

Chih-Cheng Hsieh


Compensation of Two Stage Op Amps<br />

• We identify three poles : a pole at X (or Y), another at E (or F), and a third at A<br />

(or B).<br />

• Since the poles at E and A are relatively close to the origin, the phase<br />

approaches -180 o well below the third pole.<br />

• If the magnitude of ω P,E is to be reduced, the available bandwidth is limited to<br />

approximately ω P,A , a low value. A very large compensation capacitor is<br />

required.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

22


Miller Comp. of a Two-Stage Op Amp<br />

• Create a large capacitance at node E, equal to (1 + A v2 ) C C .<br />

• The corresponding pole is moved to 1/ Rout1⎡⎣CE + ( 1+<br />

Av 2)<br />

CC<br />

⎤⎦<br />

• Miller compensation<br />

– Lowering the required capacitor value.<br />

– Moves the output pole away from the origin.<br />

• If R S denotes the output resistance of the first stage, R L = r O9 || r O11 .<br />

ω


Pole Splitting<br />

• Before compensation, ω p1 and ω p2 are<br />

of the same order of magnitude.<br />

• Miller compensation increases the magnitude of the output pole by roughly a<br />

factor of gm 9<br />

R L .<br />

• At high frequencies, C C provides a low impedance between the gate and drain of<br />

−1<br />

−1<br />

M 9 . The resistance seen by C L becomes R || g<br />

9<br />

|| R ≈ g<br />

9<br />

.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

24<br />

ω ≈ 1/[ R( C + C )] ≈1/<br />

RC<br />

p2 S E GD9<br />

L L<br />

• After compensation ,<br />

gm gm<br />

If CC + CGD9 >> CE , ω<br />

p2<br />

≈ ≈<br />

C + C C<br />

S<br />

m<br />

L<br />

m<br />

9 9<br />

E L L


Effect of Right Half Plane Zero<br />

ω < ω < ω<br />

p1 z p2<br />

• A right-half plane zero at<br />

• Numerator is<br />

ω =<br />

• The phase shift is − tan −1<br />

negative<br />

• Zero slow down the drop of magnitude.<br />

• The stability degrades considerably.<br />

( C C )<br />

/ m9 C GD9<br />

• The right half–plane zero in a two-stage<br />

CMOS op amps is a serious issue because<br />

gm is relatively small and C C is usually large.<br />

• A series resistor to eliminate the right-half<br />

plane zero.<br />

ω ≈<br />

z<br />

C<br />

C<br />

• The output stage now exhibits three poles.<br />

• To cancel the first non-dominant pole<br />

1<br />

C g R<br />

−1<br />

( 9<br />

− )<br />

C m Z<br />

( 1 − s / ωz<br />

)<br />

1<br />

z<br />

( )<br />

ω /ω z<br />

−1<br />

( g − R )<br />

m9<br />

Z<br />

g +<br />

− g C + C + C C + C<br />

= , R = ≈<br />

C C g C g C<br />

m9<br />

L E C L C<br />

Z<br />

L<br />

+<br />

E m9 C m9<br />

C<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

25


Resistor for Miller Compensation<br />

• Typically the feedback R Z is realized by a MOS transistor in the triode region.<br />

• R Z changes substantially as output voltage excursions are coupled through C C to<br />

node X, thereby degrading the large-signal settling response.<br />

• Let<br />

( ) ( )<br />

• For pole zero cancellation to occur<br />

( ) ⎛ 14<br />

C ⎞<br />

− L<br />

m<br />

m<br />

( )<br />

− ⎜ ⎟<br />

( ) ( )<br />

14<br />

( W L<br />

−1 )<br />

14<br />

( W L)<br />

V = VμC , Wthen L V V = V V , g = − ,<br />

GS13 GS 9 GS15 GS14 m14 p ox GS14 TH14<br />

RμC = ⎡<br />

⎣W L V V − R⎤<br />

⎦ , g =<br />

on15 p ox 15 GS15 TH15 on15 m14<br />

W L ID CC<br />

g = g 1 + , W L = W L W L<br />

-1<br />

( ) ( ) ( )<br />

1 1 9<br />

14 9 15 14 9<br />

W L<br />

15 ⎝ CC ⎠<br />

ID 14<br />

CC + CL<br />

15<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

26


Defining g m9 with respect to R S<br />

• Use a simple resistor for R Z and define g m9 as a resistor that closely match R Z .<br />

• Incorporating M b1 -M b4 along with R S to generate<br />

I b<br />

∝ R<br />

−2<br />

S<br />

g<br />

m9<br />

∝<br />

I<br />

D9<br />

∝<br />

I<br />

D11<br />

∝<br />

R<br />

−1<br />

S<br />

• Proper ratio-ing of R Z and R S with temperature and process variations.<br />

• Short channel effects may deviate from the square low regime and create errors.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

27


Increased Load Cap. on Step Response<br />

• In a two-stage op-amp, a higher load capacitance presented to the second stage<br />

moves the second pole toward the origin, degrading the phase margin.<br />

– The response approaches an oscillatory behavior if the load capacitance<br />

seen by the two-stage op amp increases.<br />

• In one-stage op amps, a higher load capacitance brings the dominant pole closer<br />

to the origin, improving the phase margin.<br />

– Making the feedback system more overdamped.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

28


Slewing in Two-Stage Op Amps<br />

V ≈ I t C , SR = I C<br />

out SS C SS C<br />

• For the positive slew rate, M5 must provide two currents : I SS + I 1<br />

– If M5 not wide enough to sustain I SS + I 1 in saturation, then V X drops<br />

significantly, possibly driving M 1 into triode region.<br />

• For the negative slew rate, I 1 must support both I SS and I D5 .<br />

– If I 1 = I SS , V x rises so as to turn off M5.<br />

‣ C C is charged by a constant I SS if parasitic cap.<br />

at node X are negligible.<br />

‣ The gain of the output stage makes node X a<br />

virtual ground.<br />

– If I 1 < I SS , M 3 enters the triode region and the slew rate is given by I D3 /C C .<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

29


Outline<br />

1. General Consideration<br />

2. Phase Margin<br />

3. Frequency Compensation<br />

4. Compensation of Two-Stage Op Amps<br />

5. Other Compensation Techniques<br />

Analog IC Analysis and Design 10-30<br />

Chih-Cheng Hsieh


Other Compensation Techniques<br />

• The feedforward path formed by the comp.<br />

capacitor causes a right-half plane zero.<br />

• If C C could conduct current from the output<br />

node to node X but not vice versa, then the<br />

zero would move to a very high frequency.<br />

– Inserting a source follower in series with<br />

the capacitor.<br />

−V<br />

− g V = V R + C s V = + sR C<br />

−1<br />

out<br />

( ), ( 1 )<br />

m1 1 out L L 1<br />

L L<br />

gm<br />

1RL<br />

V −V V<br />

+ I =<br />

(1 / g ) (1 / sC ) R<br />

out 1 1<br />

in<br />

m2<br />

+<br />

C S<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

31


Compensation Using Source Follower<br />

• We have<br />

V<br />

I<br />

out<br />

in<br />

=<br />

R<br />

L<br />

C<br />

C<br />

C<br />

L<br />

− gm<br />

1RLRS<br />

( gm2<br />

+ sCC<br />

)<br />

2<br />

( 1+<br />

gm2RS<br />

) s + [( 1+<br />

gm<br />

1gm2RLRS<br />

) CC<br />

+ gm2RLCL<br />

] s + gm2<br />

ω<br />

p1<br />

≈<br />

g<br />

m1<br />

( 1+<br />

g g R R )<br />

If 1+<br />

gm<br />

RS<br />

>> 1<br />

m1<br />

m2<br />

L S<br />

CC<br />

>> gm2R<br />

g<br />

2 L L<br />

gm2<br />

1<br />

gm<br />

1gm2RLRSCC<br />

gm<br />

1<br />

≈<br />

ω<br />

p2<br />

≈<br />

≈<br />

m2RLRSCC<br />

gm<br />

1RLRSCC<br />

RLCLCC<br />

gm2RS<br />

CL<br />

C<br />

• Thus, the circuit contains a zero in the left half plane, which can be chosen to<br />

cancel one of the poles.<br />

• The new values of ω , p 1<br />

ω<br />

p2<br />

are similar to those obtained by simple Miller<br />

approximation.<br />

• The source follower limits the lower end of the output voltage to V<br />

GS 2<br />

+ VI<br />

2 .<br />

• It is desirable to utilize the compensation capacitor to isolate the DC levels in the<br />

active feedback stage from that at the output.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

32


Compensation Using a CG Stage<br />

• C C and the common gate stage M 2 converts the output voltage swing to a<br />

current, returning the result to the gate of M 1 .<br />

• If V 1 changes by ∆V<br />

, V changes by A v<br />

∆V<br />

out<br />

• The current flows through the capacitor is nearly equal to Av∆VCCs<br />

because<br />

1/g m2 can be relatively small.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

33


Compensation Using a CG Stage<br />

g V sC<br />

,<br />

m2 2<br />

C<br />

Vout<br />

+ =− V2 V2<br />

=−Vout<br />

sCC sCC + gm2<br />

g V + V<br />

⎛ 1<br />

+ sC<br />

⎞<br />

= g V , I<br />

V<br />

= + g V<br />

⎝ ⎠<br />

1<br />

ω<br />

p1<br />

≈<br />

V<br />

− g<br />

out<br />

m1RSRL( gm2<br />

+ sCC)<br />

gm 1RRC<br />

L S C<br />

=<br />

2<br />

Iin RCCs<br />

L C L<br />

+ ⎡⎣( 1+ gm 1RS)<br />

gm2RC L C<br />

+ CC + gm2RC L L⎤⎦s + g<br />

g<br />

m2<br />

m2Rg<br />

S m1<br />

ω<br />

p2<br />

≈<br />

C<br />

• Contains a left-plane zero<br />

• The second pole has considerably risen in magnitude – by a factor of g m2 R S .<br />

– At very high frequencies, the feedback loop consisting of M 2 and R S lowers<br />

the output resistance by the same factor.<br />

– If the capacitance at the gate of M1 is taken into account, pole splitting is<br />

less pronounced.<br />

– This technique can potentially provide a high bandwidth in 2-stage op-amp.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

34<br />

1<br />

m1 1 out ⎜<br />

L ⎟ m2 2 in m2 2<br />

RL<br />

RS<br />

L


Slew Rate Analysis<br />

I ≥ I + I<br />

I2 ≥ ISS<br />

+ ID2<br />

1 SS D1<br />

• For positive slewing, M2 and hence I 1 must support I SS , requiring that<br />

– If I 1 < I SS + I D1 , then V p drops, turning M 1 off.<br />

– If I 1 < I SS , M 0 and its tail current source must enter the triode region,<br />

yielding a slew rate equal to I 1 /C C .<br />

• For negative slewing, I 2 must support both I SS and I D2 .<br />

– As I SS flows into P → V GS1 ↑ → I D1 ↑ → V X ↓ → P is a virtual ground node.<br />

– I 3 and I 2 must be as large as I SS , raising the power dissipation.<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

35


Alternative Comp. of 2-Stage Op-Amp<br />

• The zero appears at<br />

( g R )( g / C )<br />

m4<br />

eq<br />

m9<br />

C<br />

• The dominant pole is located at approximately<br />

• The first non-dominant pole is given by<br />

Analog IC Analysis and Design 10- Chih-Cheng Hsieh<br />

36<br />

gm4gm9<br />

C<br />

L<br />

R<br />

eq<br />

Reqgm9<br />

1<br />

R<br />

L<br />

C<br />

C

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