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408 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 5, MAY 2010
PBTI/NBTI-Related Variability in
TB-SOI and DG MOSFETs
B. Cheng, A. R. Brown, Member, IEEE, S.Roy,andA.Asenov,Senior Member, IEEE
Abstract—We study positive bias temperature instability/
negative bias temperature instability (PBTI/NBTI)-related agingdependent
statistical variability (SV) in 32-nm thin-body
silicon-on-insulator (TB-SOI) and 22-nm double-gate (DG)
MOSFETs using comprehensive 3-D numerical simulation.
Results indicate that a high degree of PBTI/NBTI degradation
can introduce a similar level of SV as the variability in the initial
“virgin” devices introduced by random discrete dopants and
line edge roughness. Simulations have shown that the TB-SOI
and the DG MOSFETs have different susceptibilities to
PBTI/NBTI-induced variability.
Index Terms—Double gate (DG), MOSFETs, positive bias
temperature instability/negative bias temperature instability
(PBTI/NBTI), SOI, statistical variability (SV).
I. INTRODUCTION
STATISTICAL variability (SV), arising from the discreteness
of charge and granularity of matter, has become one
of the major challenges to CMOS scaling and integration [1].
The major source of static SV in conventional (bulk) MOSFETs
is the random discrete dopant (RDD) in the channel region.
New device architectures with better electrostatic integrity,
such as thin-body silicon-on-insulator (TB-SOI) or doublegate
(DG) MOSFETs that can tolerate low channel doping
concentration, will be required in the near future in order to
keep the SV under control [2]. On the other hand, scalingrelated
statistical reliability issues exacerbated by the introduction
of high-κ gate stacks start to negatively impact the aging
resilience of integrated circuits [3]. Negative bias temperature
instability/positive bias temperature instability (NBTI/PBTI) is
the dominant mechanism that results in time-dependent degradation
of the transistor characteristics [4]. The NBTI/PBTI is
associated with discrete charge trapping at, or in the vicinity
of, the interface that results in an increase in the SV [5], [6].
NBTI/PBTI-related variability can rapidly erode the SV advantages
of “virgin” TB-SOI and DG MOSFETs. In this letter, we
employ comprehensive 3-D statistical simulations to evaluate
the impact of NBTI/PBTI on the SV of 32-nm TB-SOI and
22-nm DG LSTP MOSFETs.
Manuscript received January 19, 2010. Date of publication March 22, 2010;
date of current version April 23, 2010. This work was supported in part by
the European Union through the EP6 Integrated Project PULLNANO, by the
FP7 Network of Excellence NANOSIL, and by the U.K. EPSRC NANOCMOS
Project. The review of this letter was arranged by Editor A. Ortiz-Conde.
The authors are with the Department Electronics and Electrical Engineering,
University of Glasgow, G12 8LT Glasgow, U.K. (e-mail: B.Cheng@
elec.gla.ac.uk; A.Brown@elec.gla.ac.uk; S.Roy@elec.gla.ac.uk; A.Asenov@
elec.gla.ac.uk).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2010.2043812
II. DEVICE SETUP AND SIMULATION METHODOLOGY
A. Device Structures
The investigated devices are 32-nm physical gate length TB-
SOI and 22-nm physical gate length DG template nMOSFETs
developed by the PULLNANO consortium. The device structures
and doping profiles are presented in the insets of Fig. 1.
Both devices feature a TiN metal gate with a HfO 2 /SiO 2 high-κ
gate dielectric with effective oxide thicknesses of 1.2 and
1.1 nm, and silicon body thicknesses of 7 and 10 nm, respectively.
The buried oxide (BOX) thickness of the TB-SOI device
is 20 nm. The channel doping concentration for both devices is
1.2 × 10 15 cm −3 , and the junction-to-junction effective channel
lengths are 13 and 8 nm, respectively. Only n-channel devices
and the corresponding PBTI variability are simulated in this
letter, but we expect that the effects in p-channel transistor
under NBTI will be analogous.
B. Simulation Methodology
The Glasgow 3-D “atomistic” drift–diffusion simulator with
simultaneous density-gradient quantum corrections for electrons
and holes is employed in this study [7]. RDD and line edge
roughness (LER) are considered as the main sources of SV in
the “virgin” devices. Previous studies show that the impact of
statistical body thickness variation due to atomic scale interface
roughness is negligible in devices with body thickness above
7 nm [8]. Also, although the granularity of the metal gate and
corresponding work-function variations could be an important
source of SV in metal gate devices [9], in this letter, we consider
amorphous TiN which is technologically achievable [10]. The
rms amplitude of LER in the simulations is 1.3 nm, and the
correlation length is 25 nm. The sheet density of trapped charge
introduced by PBTI/NBTI is determined by the electric/thermal
stress pattern and the aging conditions of the device, and by
the processing and the material properties of the high-κ/metal
gate stack. Our simulations are frozen in time and consider the
variability associated with different levels of uniform Trappedcharge
Sheet Density (TSD) corresponding to different stages
of the PBTI/NBTI degradation. Three TSDs—1 × 10 11 ,5×
10 11 , and 1 × 10 12 cm −2 are selected to represent the early,
intermediate, and later aging stages. Assuming that charges are
trapped at the Si/SiO 2 interface, a fine auxiliary 2-D mesh is
imposed at the interface. A rejection technique is used at each
node of this mesh to determine if a single positive charge is
located at that node or not based on the TSD. If it is determined
that a single charge should be placed there, then its electronic
charge is assigned to the surrounding nodes of the 3-D
discretization mesh using a cloud-in-cell charge assignment
scheme. As a result, both the number of trapped charges and
0741-3106/$26.00 © 2010 IEEE

CHENG et al.: PBTI/NBTI-RELATED VARIABILITY IN TB-SOI AND DG MOSFETs 409
Fig. 2. Normal probability plot of the fractional threshold voltage change due
to PBTI under various TSD scenarios for the TB-SOI device with combined
static SV.
Fig. 1. Threshold voltage variation introduced by individual SV sources.
(a) 32-nm TBSOI. (b) 22-nm DG device. (Inset) Device structures.
their individual positions are different from device to device.
For each TSD level, a statistical sample of 200 microscopically
different devices is simulated.
III. RESULTS AND DISCUSSION
To simulate the standard deviation of the threshold voltage
(σV th ), a V th current criterion of 1 μA/μm is used. The impact
of individual SV sources on σV th is shown in Fig. 1.
Due to the low channel doping, the RDD variability is greatly
reduced, yielding σV th of 5 and 7 mV for the TB-SOI and
DG MOSFETs, respectively, at a V DS of 1 V. LER is the
main source of SV in these devices, exhibiting strong bias
dependence. The LER-induced σV th increases from 6 to 9 mV
in the TB-SOI and from 11 to 16 mV in the DG device with
V DS increasing from 50 mV to 1 V. The TSD in Fig. 1 is
5 × 10 11 cm −2 with trapped charge assigned only at the top
interface for TB-SOI, while for DG device, both top and bottom
gate interfaces have the same TSDs. σV th is close to 12 mV
for both devices, and this value is comparable to the variation
introduced by the combined effect of RDD and LER.
It could be expected that, in the TB-SOI case, the PBTI
will happen dominantly at the top interface. However, the BOX
interface usually does not have the same quality as gate oxide,
and a higher intrinsic defect density can be expected at the back
interface. Due to the lack of experimental data for the TSD at
the BOX interface during the aging process, three scenarios are
Fig. 3. Normal probability plot of threshold voltage under the influence of
combined static SV sources with different TSDs.
considered in this letter: Scenario 1 assumes that there is no
trapped charge at the BOX interface; scenario 2 assumes that,
during the aging process, the TSD at the BOX interface has only
the initial defect density fixed at 1 × 10 11 cm −2 ; and scenario 3
assumes identical TSDs at the top and BOX interfaces. Fig. 2
shows the distribution of the fractional threshold voltage
changes ΔV th due to the trapped charge in the simultaneous
presence of RDD and LER for the three scenarios. Although
scenario 3 is an extreme setting that may not occur in a real case,
it illustrates that, for a thin BOX structure, the quality of the
BOX interface has a first-order impact on device characteristics
due to charge coupling [11].
In the rest of this letter, scenario 2 is adopted for the TB-
SOI MOSFET. Fig. 3 shows the impact of TSD on threshold
voltage distribution at a V DS of 1 V, clearly demonstrating
significant departures from the normal distribution represented
with straight lines. As expected, the mean value of threshold
voltage (μV th ) depends linearly on TSD. σV th increases nonlinearly
with TSD but the increase is much faster in the TB-SOI
transistor.
The distributions of ΔV th for the TB-SOI and DG transistors
at different stages of PBTI degradation are shown in Fig. 4. At
each increased level of degradation, PBTI introduces large and
widespread threshold voltage changes. Although the TB-SOI
transistor has a larger gate area, at each level of degradation, the
corresponding fractional changes are larger and more widely

410 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 5, MAY 2010
Fig. 4. Normal probability plot of the increase of threshold voltage due to PBTI for 32-nm TB SOI and 22-nm DG devices. (Inset) Carrier density distribution at
threshold voltage.
LER. The effect is much stronger in the 32-nm TB-SOI case
with lower initial variability, where a TSD of 1 × 10 12 cm −2
results in almost twofold increase in σV th . The same amount of
TSD in the DG case results in less than 30% increase in σV th .
The improvement is related to volume inversion in the DG case.
Fig. 5. Potential profiles of (a) TB SOI, (b) DG devices with combined RDD
and LER at a TSD of 1 × 10 12 cm −2 . The potential profile slices are cut at a
location where maximum carrier density occurs.
distributed compared to the DG case. Although its effective
gate area is 60% smaller than its TB-SOI counterpart, the
DG MOSFET is clearly less susceptible to PBTI-induced
variability.
The inset of Fig. 4 shows the charge distribution between
the top and bottom interfaces of the TB SOI and the DG
MOSFETS. In the DG case, volume inversion [12] occurs,
and the carriers flow close to the center of the device where
the potential fluctuations introduced by the trapped charges are
relatively small, resulting in a lower variability compared the
TB-SOI where the transport occurs close to the top interface.
This, however, means that, in the DG case, the current flow
is equally influenced by the trap charges at both interfaces
(effectively doubling the TSD) in the DG device; thus, there
is no reduction in variability due to averaging, as may be the
case with two independent channels.
The different magnitudes of the potential fluctuations at the
position of the dominant current flow for the DG and TB SOI
transistors are shown further in Fig. 5. The channel potential
landscape (the top plot in each device) is visibly smoother in
the DG case compared to the TB-SOI case.
IV. CONCLUSION
The results of this letter have indicated that, in TB-SOI
and DG MOSFETs, PBTI/NBTI degradation can significantly
increase the initial “virgin” variability coming from RDD and
REFERENCES
[1] A. Asenov, S. Roy, R. A. Brown, G. Roy, C. Alexander, C. Riddet,
C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M. F. Bukhori,
X. Wang, and U. Kovac, “Advanced simulation of statistical variability
and reliability in nano CMOS transistors,” IEDM Tech. Dig., p. 1, 2008.
[2] [Online]. Available: http://www.itrs.net/
[3] J. C. Liao, Y. K. Fang, Y. T. Hou, C. L. Hung, P. F. Hsu, K. C. Lin,
K. T. Huang, T. L. Lee, and M. S. Liang, “BTI reliability of dual metal
gate CMOSFETs with HF-based high-κ gate dielectrics,” in Proc. VLSI-
TSA, 2007, pp. 1–2.
[4] S. Mitra, “Circuit failure prediction for robust system design in scaled
CMOS,” in Proc. IEEE IRPS, 2008, pp. 524–531.
[5] V. Huard, C. Parthasarathy, C. Guerin, T. Valentin, E. Pion,
M. Mammasse, N. Planes, and L. Camus, “NBTI degradation: From
transistors to SRAM arrays,” in Proc. IEEE 46th Annu. Int. Reliab. Phys.
Symp., 2008, pp. 289–300.
[6] S. E. Rauch, “Review and reexamination of reliability effects related to
NBTI-induced statistical variations,” IEEE Trans. Device Mater. Rel.,
vol. 7, no. 4, pp. 524–530, Dec. 2007.
[7] A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, “Increase
in the random dopant induced threshold fluctuations and lowering
in sub-100 nm MOSFETs due to quantum effects: A 3-D density gradient
simulation study,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 722–
729, Apr. 2001.
[8] B. Cheng, S. Roy, A. R. Brown, C. Millar, and A. Asenov, “Evalution
of statistical variability in 32 and 22 nm technology generation LSTP
MOSFETs,” Solid State Electron., vol. 53, no. 7, pp. 767–772, Jul. 2009.
[9] H. Dadgour, De Vivek, and K. Banerjee, “Statistical modeling of metalgate
work-function variability in emerging device technologies and implications
for circuit design,” in Proc. Int. Conf. CAD, 2008, pp. 270–277.
[10] K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita,
T. Chikyow, K. Shiraishi, Y. Nara, and K. Yamada, “Impact of additional
factors in threshold voltage variability of metal/high-κ gate stacks and its
reduction by controlling crystalline structure and grain size in the metal
gates,” in IEDM Tech. Dig., 2008, pp. 409–412.
[11] V. P. Trivedi and J. G. Fossum, “Nanoscale FD/SOI CMOS: Thick or thin
BOX?” IEEE Electron Device Lett., vol. 26, no. 1, pp. 26–28, Jan. 2005.
[12] L. Ge, J. G. Fossum, and F. Gamiz, “Mobility enhancement via volume
inversion in double-gate MOSFETs,” in Proc. IEEE Int. SOI Conf., 2003,
pp. 153–154.