Reliability Simulation in Integrated Circuit Design - Cadence ...

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RELIABILITY SIMULATION IN INTEGRATED CIRCUIT DESIGN

TABLE OF CONTENTS
1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 HCI and NBTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Stress measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Extraction and modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 New flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Reliability circuit simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Design challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE OF FIGURES
Figure 1 HCI on NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 NBTI on PMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 BSIMProPlus/RelProPlus and its measurement environment . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 4 Stress conditions setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 5 Measurement setup conditions during the stressing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 6 Device degradation monitor Idlin, Idsat, Vt, and Gmmax parameters vs. the stress time . . . . 3
Figure 7 NMOS extraction steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 8 PMOS extraction steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 9 Lifetime modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 10 Reliability model iterations for improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 11 Ring oscillator schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 12 Reliability simulation with Virtuoso UltraSim or RelXpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 13 Virtuoso UltraSim Full-chip Simulator GUI inside the Virtuoso Analog Design Environment . . 7
Figure 14 Backannotation of the lifetime and degradation into the schematic. . . . . . . . . . . . . . . . . . . . 7
Figure 15
Result of fresh and aged simulation using Virtuoso UltraSim Full-chip Simulator
and displayed in AWD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1 ABSTRACT
As gate oxide thickness and dimensions of scale shrink in integrated circuit design, reliability problems
occur and need to be considered early in the design process. Some of the more problematic issues include
negative bias temperature instability (NBTI) and hot carrier injection (HCI). NBTI is a critical factor in PMOS
devices and leads to current degradation, yield loss, and functional failure of integrated circuits. HCI has
primarily effected NMOS devices, but today it is also a concern for PMOS devices. HCI is caused by hot
carriers in the gate oxide that lead to oxide damages, which manifest themselves as current degradation,
Vt shift, leakage current increase, etc.
Over time, both NBTI and HCI degrade device currents and will cause failures in integrated circuits. Circuit
designers need to consider these reliability effects in the early stages of design to make sure there are
enough margins for circuits to function correctly over their entire lifetime. Cadence ® provides a complete
solution, including reliability model extraction and calibration to silicon, with Virtuoso Device Modeling
(BSIMProPlus) and full-chip reliability simulation and analysis with Virtuoso ® UltraSim Full-chip Simulator.
2 INTRODUCTION
CMOS technologies are constantly scaled down. For example, before the end of 2003, microprocessors will
be produced on 90 nm processes, and production on 65 nm is planned for 2005. With the reduction in
geometries, the devices become more vulnerable to HCI and NBTI. With its recent acquisition of Celestry,
Cadence offers the benefit of more than 8 years of experience in reliability modeling and circuit
simulations in its flows. This paper presents an overview of this new reliability flow and offers suggestions
to enhance HCI/NBTI circuit robustness.
3 HCI AND NBTI
With the geometric scale down, HCI and NBTI problems become worse. In the channel of the MOS, a high
electrical field is created close to the drain. The gate oxide thickness is also reduced to allow low
threshold voltages. When the channel is conducting (Figure 1), the high electrical field close to the drain
generates an injection of hot carriers into the (SiO2) gate oxide layer. This inserts charges in the oxide by
trapping carriers (electrons and holes). These carriers can cause permanent changes in the oxide-interface
charge distribution.
S
G
I
g
D
n+
n+
P-well
I sub
impact
ionization
oxide
damage
Figure 1: HCI on NMOS
1

This can also degrade the device’s drain current capability. The accumulation of trapped charge will lower
saturation current Idsat, cause Vt drift, lower the linear region transconductance, and degrade the
subthreshold slope. As the geometry scales down, these problems become worse. Some IC manufacturers
have already reported HCI problems for 0.5 um processes.
NBTI is a critical effect in PMOS (see Figure 2). Some carriers damage the oxide, especially in processes
where the oxide thickness is less than 50 angstroms. This is usually the case for 0.13 µ CMOS.
S
G
D
p+
p+
N-sub
Figure 2: NBTI on PMOS
4 STRESS MEASUREMENTS
Virtuoso Device Modeling (BSIMProPlus/RelProPlus) automates HCI and NBTI stress and data collection
through simultaneous control of various measurement hardware (see Figure 3). We can stress multiple
devices at the same time.
BSIMProPlus
RelProPlus
DC Source 1
Probe station
DC Source 2
DC Source n
I-V Meter
Figure 3: BSIMProPlus/RelProPlus and its measurement environment
2

We configure the devices we want to stress and we specify the bias stress conditions and the total
stress time (see Figure 4).
Figure 4: Stress conditions setup
During stress, BSIMProPlus/RelProPlus can conduct the following measurements, as shown in Figure 5:
• Device IV curves, to observe how the device operation characteristics change over time.
These collected curves will be used for the AgeMos modeling stage.
• Degradation monitors. We observe the degradation of important circuit variables.
Figure 5: Measurement setup conditions during the stressing time
We see in Figure 6 that transistor degradation is a function of stress time. For these devices, we have four
figures. For each of them the X axis is the stress time. Idlin and Idsat are decreasing, Vt is increasing, and
Gmmax is decreasing.
Figure 6: Device degradation monitor Idlin, Idsat, Vt, and Gmmax parameters vs. the stress time
3

5 EXTRACTION AND MODELING
For the NMOS, the extraction starts from the fresh model card (see Figure 7). We can start, for example,
from existing BSIM3 or BSIM4 model cards. To these NMOS parameters we add some parameters for
accurate Isub modeling. Using one of the monitoring data measurements — Idsat or Idlin or Vt or
Gmmax — we perform the lifetime extraction. The last step is AgeMos extraction. The AgeMos allows
degradation models, which can run into any SPICE-like simulators, for the aged simulation.
Fresh model card
Isub model
Lifetime model
HCI AgeMos model
Figure 7: NMOS extraction steps
For PMOS extraction, the difference is the addition of NBTI parameters extraction in the flow (see
Figure 8). Gate current, instead of substrate current, modeling may be used for age prediction.
Fresh model card
Isub/Igate model
Lifetime model
NBTI AgeMos model
I-CI AgeMos model
Figure 8: PMOS extraction steps
The extraction of the lifetime parameters is easily performed. In Figure 9, we selected Idsat for lifetime
monitoring. The Idsat measurement shows that we have a current degradation versus the stress time.
Idsat is a classical degradation monitor for digital applications. For analog application we usually prefer
the threshold voltage Vt.
4

Figure 9: Lifetime modeling
The AgeMos model makes it possible to have degradation models based on the age calculated after the
fresh simulation. The Virtuoso UltraSim Full-chip Simulator can use these models directly. To run aged
simulation with other commercial simulators, such as the the Virtuoso Spectre ® Circuit Simulator, we will
use a Cadence technology called RelXpert.
Reliability modeling is an iterative process. Sometimes you need several iterations to get an accurate model,
as shown in Figure 10.
Fresh model card
Isub/Igate model
Lifetime model
AgeMos model
Yes
Improvement
End
No
Figure 10: Reliability model iterations for improvements
6 NEW FLOW
For many companies, the existing reliability flow is defined by rules: The reliability department defined
reliability constraints that must not be violated by designers. Checking the reliability of HCI/NBTI simulation
is performed on the finished chip after burning the first prototypes. When failure occurs, a complete
redesign must be done. The time-to-market of the circuits is delayed by six months or more…
The new flow introduces reliability circuit simulation in the circuit design phase, prior to layout.
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7 RELIABILITY CIRCUIT SIMULATION
The traditional method to verify reliability models is to use a ring oscillator. We have selected a ring
oscillator with nine inverters. The schematic has been entered in the Virtuoso Schematic Editor
(Figure 11).
Figure 11: Ring oscillator schematic
For the circuit simulation we can use one of two solutions — the Virtuoso UltraSim Full-chip Simulator or a
SPICE-like commercial simulator such as the Virtuoso Spectre Circuit Simulator.
INPUT SIMULATION OUTPUT
Schematic
SPICE netlist
SPICE model
Reliability param
Reliability spec
HSPICE, ELDO
& Virtuoso
Spectre
RelXpert
Virtuoso
UltraSim
• Device deg. table
• Isub/Id table
• Waveform comp.
Fresh vs. aged
BSIMProPlus
&
RelProPlus
RelLink
Schematic
Figure 12: Reliability simulation with Virtuoso UltraSim or RelXpert
The SPICE-like simulator does not have HCI and NBTI simulation. In this case, we use RelXpert. RelXpert
will drive the commercial SPICE-like simulator for the lifetime and degradation computations. RelXpert
will generate a new netlist allowing an aged circuit simulation.
Virtuoso UltraSim offers the advantage of being a FastSPICE isomorphic simulator. It can easily handle
larger circuits for mixed-signal and digital applications. For example, Virtuoso UltraSim can simulate
memories like 1GB DRAM, with more than one billion transistors. The HCI/NBTI circuit simulation is built
inside Virtuoso UltraSim. Figure 13 shows a snapshot of Virtuoso UltraSim Full-chip Simulator integration
with the Virtuoso Analog Design Environment.
6

Figure 13: Virtuoso UltraSim Full-chip Simulator GUI inside the Virtuoso Analog Design Environment
With the reliability simulation we can:
• Ask for the prediction of the age of each MOS instance.
• Request the simulator to predict degradation after several years of operation, for example 10 years, and
also to generate degraded transistor models after 10 years of operation.
• Request a lifetime prediction for each transistor, under the circuit operation condition, to reach a certain
percentage of degradation. 10% degradation is a common request for reliability.
• Select both HCI and NBTI at the same time, HCI only, or NBTI only, to get an aged simulation with
degradation.
In this simulation, computing the age of each MOS instance is key information. For example, NMOS age is
calculated with the following formula:
Age (t) =
”(
t
I
)
sub ()
o
I ds
()
m
I ds ()
HW
The simulator will print out the degradation results in a table or with schematic backannotation
(see Figure 14).
Figure 14: Backannotation of the lifetime and degradation into the schematic. In this example the lifetime is bad.
7

This age information is used by the AgeMos to predict HCI and NBTI degradation, as shown in Figure 15.
Figure 15: Result of fresh and aged simulation using Virtuoso UltraSim Full-chip Simulator and displayed in AWD.
The period of the oscillator is increased.
Note: Virtuoso UltraSim and RelXpert can also be used as standalone products, outside the Virtuoso
Analog Design Environment.
8 DESIGN CHALLENGES
HCI and NBTI introduce a threshold voltage increase for the MOS. This may be a real issue for mixedsignal
applications. There is also a gm transconductance variation. This characteristic changes the gain of
transistors, which may not be expected by analog designers.
With HCI and NBTI circuit simulation, designers can detect and locate potential issues.
Because HCI is dependant of the horizontal electrical field in the channel, designers can improve the
robustness of the devices by increasing their length. There is also an exponential decrease in hot carriers
with a decrease in supply voltage. Designers can change the bias conditions of the devices where the issue
is found.
NBTI problems are more difficult to fix. Designers can check voltage overshoot to avoid the damage
caused by NBTI. They may decide to increase capacitive loads, increase the transconductances, or reduce
the supply voltage of the function to reduce NBTI susceptibility.
Designers should make it a priority to study the IO blocks of their designs. Creating robust HCI/NBTI
circuits is a new challenge for digital/analog designers.
9 CONCLUSION
A complete flow allowing digital and analog designers to compute HCI and NBTI reliability circuit
simulation is available. Reliability circuit simulations are now possible: block reliability analysis can be
conducted with RelXpert driving commercial simulators, and SOIC analysis is run with the new Virtuoso
UltraSim Full-chip Simulator. HCI/NBTI reliability is a must for designs implemented with new processes.
Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. Cadence
offers a modeling service and can train the company modeling team on HCI/NBTI measurement and
parameter extraction.
Designers need to learn to design for reliability and they should be educated on additional reliability
analyses. The value is the reduction of failure and redesign costs.
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#5082 12/03