c-Si PVMC Brief Overview

c‐Si PVMC Brief Overview
Intersolar NA –San Francisco, CA
Dr. Winston V. Schoenfeld
Director, c‐Si PVCM
July 10 th , 2012
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U.S. Department of Energy and may not be published, disseminated, or disclosed to others outside the Government until five (5)
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DOE SunShot Initiative
• Mission of DOE SunShot Initiative
- Deliver grid-parity solar PV by 2020, a goal that will demand
~75% reduction in the cost of systems compared with today
- Restore US leadership in the global clean energy race
• SunShot Photovoltaic Manufacturing Initiative (PVMI) - $110M
• PV Cells / Modules – 3 recipients
Balance of System
Power Electronics
• April 2011 – award recipients of solar cell/module
- Industry-led consortium, SEMATECH – PVMC
Copper indium gallium selenide (CIGS) pilot line, in partnership with CNSE
c-Si metrology and feedstock/wafering technologies, in partnership with UCF/FSEC in Florida
- PV manufacturing development facility – SVTC
- University-led consortium – BAPVC (Stanford/Berkeley)
U.S. Photovoltaic Manufacturing Consortium (PVMC)
Consortium
Management
CIGS
c‐Si
2

c‐Si PVMC Program Areas
& Structure

Initial c‐Si PVMC Program Areas
1. In‐line/Off‐line Metrology
Primary Goals
– Identify critical industry challenges/needs in metrology and rank
– Participate and support c‐Si standards development and roadmapping efforts
– Develop projects to demonstrate new c‐Si metrology technologies
– Build infrastructure to support metrology programs
– Transition new metrology technologies into pilot and manufacturing lines
Courtesy of Polaritek
2. New Feedstock/Wafering Methodologies
Primary Goals
– Identify critical industry needs in feedstock and metrology
Courtesy of AMAT
– Establish c‐Si feedstock/wafering programs to accelerate transition of new technologies into mainstream manufacturing
– Provide/foster process, test, and demonstration activities to validate new technologies and identify barriers
– Participate and support c‐Si standards development and roadmapping efforts

The c‐Si PVMC Organizational Structure
‐ Oversight of all c‐Si PVMC programs and personnel
‐ Strategic planning and expansion
‐ Management of program areas
‐ Coordination of program area
activities
Program Area Oversight
‐ Sets Program Area priorities
‐ Selects consortium projects and resource allocation
‐ Reviews program area directions/deliverables/milestones
‐ Populated by Consortium Members
Project Area Oversight
‐ Identifies potential Program Area projects
‐ Ranks potential Projects through Pareto analysis
‐ Sets Project goals/metrics/deliverables
‐ Carries out Project tasks, populated with Assignees
‐ Leads Roadmapping and Standards Development
Key Point: Programs are initiated, monitored, and measured by PVMC members

c‐Si PVMC Activities Timeline
Identify Challenges
Identify Projects
Select
Projects

c‐Si Challenges Pareto Results
Identify Challenges
Identify Projects
Select
Projects

c‐Si PVMC Challenges Pareto Effort
Code
W-C1
W-C2
W-C3
W-C4
Wafer Production Area Challenges
Thin wafers handling and processing (e.g. limiting breakage); Thin wafer
interconnection; Test methods or a specific handling target to
characterizate/validate handling for thin wafers; Pre-processing, handling, and
packaging/shipment of thin wafers to cell manufacturer
Slurry recycling
Reduction of kerf loss
Unified incoming wafer specifications and standards; Better specifications for
mechanical and electrical characterization (Affects cell effiency & end product
performance)
Grain boundary passivation of multicrystalline Si wafers
W-C5
W-C6 Determination of electrical activity of crystallographic defects in a wafer
W-C7 Understanding critical crack lengths vs. wafer thickness
W-C8 Wafer consistancy
Lack of detailed information from customers (only pass/fail info given); Lack of
W-C9
US based solar companies for partnerships
W-C10 Saw damage removal and surface characterization
New wafering technologies (kerf-free, implan/cleave, direct wafer technology ,
W-C11
etc.); Lower cost SOI wafers
W-C12 Correlation of reliability/degradation mechanisms to wafer quality/properties
Decoupling bulk and surface recombination in carrier lifetime measurement;
W-C13 Carrier lifetime measurements at the wafer level, better prediction of cell
efficency
In-line inspection of wafers; Determine optimal scan density and cost versus
W-C14
need (value-cost curve)
Unknown impact of new wafer formats (ex. quasi-mono wafers, n-type wafers,
W-C15
etc.) on cleaning and texturing processes
PVMC Confidential –Not for reproduction/distribution without written permission from PVMC‐FL

c‐Si Potential Projects Pareto Results –
Effort undertaken after Challenges
Pareto
Identify Challenges
Identify Projects
Select
Projects

M‐P1
Goals and Main
Objectives
Expected Duration
Challenge Addressed
Brief Description
Example Metrology Project Description
Improved methods of characterizing mechanical integrity of wafers/cells and
identifying wafers that might lead to high breakage
• More reliably detect what wafers/cells might lead to cracks before, during and
after processing (i.e. go/no‐go criteria)
• Gain further understanding of the key process steps and handling issues that
induce cracks (externally applied stress)
• Improve accuracy and reliability of residual stress/strain and crack detection
measurements for various sample types
• Develop in‐line methods for measuring elastic properties of wafers/cells
• Improved manufacturing yield for thin and standard thickness wafers/cells
• Potential β‐site demonstration of in‐line cell metrology tool(s)
2‐3 years
Primary: W‐C1, W‐C7, FW‐C7, FW‐C8, C‐C1, M‐C8, MCC‐C7, MCC‐C10
Secondary: W‐C4, W‐C12, W‐C14, FCC‐C5, C‐C6, C‐C12, MCC‐C4, MCC‐C8
A statistically relevant number of incoming wafers (thin and standard thickness) are
processed in lots with various process parameters and handling methods, with in‐line
measurements (RUV, optical) performed at various points (beforehand and during
critical process/handling steps). Failures are inspected using established off‐line
methods (SAM, X‐ray based, optical, Kelvin probe). Stress tests (thermal cycling,
mechanical impact, test‐to‐failure methods) are carried out on cells along with
additional characterization. Models are developed and refined to provide go/no‐go
criteria for breakage. A smaller sample size of wafers is fully characterized before,
during and after processing to more thoroughly investigate the evolution of the
stress/strain profiles throughout processing and refine models.
Challenges in RED were among top three challenges for that production area.
PVMC Confidential –Not for reproduction/distribution without written permission from PVMC

c‐Si PVMC Potential Projects Pareto Effort
PVMC Confidential –Not for reproduction/distribution without written permission from PVMC

c‐Si PVMC Membership
Identify Challenges
Identify Projects
Select
Projects

Membership Process Timeline

c‐Si PVMC Membership Levels
Two Membership Levels:
– Full Members
• TAB seat in both Program Areas
• Working Group Participation
• Access to/participation in all Program Areas (Metrology,
Feedstock/Wafering, etc.)
• Full IP access
– Program Members
• TAB Participation in designated Program Area (Designated in Attachment
A of Participant Agreement)
• Working Group Participation in designated Program Area
• Access to/participation in designated Program Area
• IP access within designated Program Area

c‐Si PVMC Calendar of Events

2012 c‐Si US PVMC Events Calendar
Date Event Format Amplification
JAN 1/11 and 1/12 Kick-off meetings WebEx/telecon Identify/list key challenges
FEB
2/1 and 2/2 Follow-up Meetings WebEx/telecon Review Pareto results for challenges
2/7/2012 Conference - Washington, DC DOE Metrology Workshop Networking
MAR 3/7 and 3/8 Working Group Face to face meeting Identify projects for Pareto analysis
4/12/2012 Working Group WebEx/telecon Review Pareto and provide comments
APR
NREL-PVMC Projects
4/25/2012 John Wohlgemuth - NREL WebEx/telecon
Review Papers/Standards
5/3/2012 SEMATECH-PVMC Meeting Face to face meeting Progress Status
MAY
5/7/2012 Carl Osterwald - NREL WebEx/telecon Standards
5/8/2012 Larry Sherwood – Solar ABCs WebEx/telecon Standards
5/25/2012 Workshop Committee WebEx/telecon Select Technical Program
JUN
6/6/2012
Standards kick-off meetings
Conference - Austin, TX
IEEE PVSC
5pm – 8:30pm
Networking
Working Group WebEx/telecon Project execution and review
6/13 and 6/14
DOE Forum Poster session Showcase c-Si PVMC
7/10
Feedstock/Wafering Workshop
7/11 Conference – San Francisco, CA
Intersolar NA
Networking
7/12
Metrology Workshop
JUL
7/25/12
Conference - Vail, CO
Roadmap kick-off meeting
7/25/12
NREL c-Si Workshop
Networking
7/26/12
Golden, CO
NREL Visit
AUG 8/8 and 8/9 Working Group WebEx/telecon Project execution and review
9/10/12
Face to face meetings
SEP to
Conference - Orlando, FL Solar Power International
SDOs Forum
9/13/12
Networking
OCT 10/10 and 10/11 Working Group WebEx/telecon Project execution and review
NOV 11/14 and 11/15 Working Group WebEx/telecon Project execution and review
DEC 12/12 and 12/13 Working Group WebEx/telecon Project execution and review

c‐Si PVMC Standards Kick‐off Meeting
IEEE PVSC – Austin, TX – Wednesday 6/7/2012 5pm – 8:30pm
• Q: How can we better integrate c‐Si USPVMC standard efforts with
existing SDO activities –What is its role?
– c‐Si PVMC Role: Participate, not re‐create!
– Invited representatives from SDOs to participate
• >30 Participant Attended/Actively Participated
– SEMI, IEC, ASTM, Solar ABCs, NREL, UL, and Industry
• Discussion Topics
– Overview of existing SDOs/WGs/TFs/standards potentially
related to c‐Si PVMC Programs
– Identify gaps in standards that c‐Si PVMC can facilitate
– Identify specific ways c‐Si PVMC can engage w/ SDOs

c‐Si Report Generated to Document Findings/AIs
• Documents attendees, discussions, findings, and action items.

c‐Si PVMC Roadmaps Kick‐off Meeting
NREL c‐Si Workshop at Vail, CO
Wednesday 7/25/2012 1pm –4pm
• Identify and discuss existing c‐Si roadmaps
– Which ones are out there?
– Who owns them?
• Do they cover the two program areas appropriately? Identify
potential gaps/needs
• Discuss what elements are key in making a roadmap attractive
to the industry so that it is accepted and embraced by
industry