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Multi master synchronization Start Sc1 T0 Primary Master Start Sc2 Start Sc3 Start Sc4 T0 T0 T0 ! Targeted for high channel count, high throughput speed applications that go beyond 6.5MS/s (or 3.5MS/s in master/slave) ! First delivery: Techspace Aero ! Perfect clock synchronization (like with M/S) ! Plus: perfect data synchronization (like with M/S) ! Implementation: primary master and secondary master(s) ! Connection: serial link, ring topology ! SC316 only Secondary Master Secondary Master Secondary Master 26 Aerospace Testing Expo 2005
IRIG-B ! GPS based time encoding for industrial applications ! IRIG-B support in SCADAS III: ! Digital phase-lock-loop derives the system clock from the 1pps. signal " perfect clock synchronization between different front-ends ! Absolute time annotation of acquired data samples " perfect data synchronization between different front-ends ! Implementation: SCADAS III input module that combines tacho inputs with IRIG-B input 27 Aerospace Testing Expo 2005
- Page 1 and 2: AERO-ENGINE DYNAMIC TESTING tacklin
- Page 3 and 4: Jet engines: powered by a turbine e
- Page 5 and 6: Jet Engine Jet engine = turbine + t
- Page 7 and 8: Outline ! Introduction to Jet Engin
- Page 9 and 10: Traditional aero-engine dynamic dat
- Page 11 and 12: Challenges for the future Quality !
- Page 13 and 14: Challenges for the future Multi-cha
- Page 15 and 16: Processing Storage The ideal aero-e
- Page 17 and 18: Networked data acquisition system w
- Page 19 and 20: The LMS SCADAS III family The indus
- Page 21 and 22: LMS SCADAS III: a wide range of sig
- Page 23 and 24: New conditioner: PQDCA ! Programmab
- Page 25: Dynamic strain measurements ! Stand
- Page 29 and 30: Test laboratory concept Embedded wo
- Page 31 and 32: Scalable Storage NAS or SAN Gibabit
- Page 33 and 34: Data organization and retrieval Tes
- Page 35 and 36: Example 1: 200 channel recording an
- Page 37 and 38: Example 2: Physical infrastructure
- Page 39 and 40: Outline ! Introduction to Jet Engin
- Page 41: Thank you for your attention LMS Us
IRIG-B<br />
! GPS based time encoding for industrial<br />
applications<br />
! IRIG-B support in SCADAS III:<br />
! Digital phase-lock-loop derives the<br />
system clock from the 1pps. signal "<br />
perfect clock synchronization between<br />
different front-ends<br />
! Absolute time annotation of acquired data<br />
samples " perfect data synchronization<br />
between different front-ends<br />
! Implementation: SCADAS III input module<br />
that combines tacho inputs with IRIG-B input<br />
27 Aerospace Testing Expo 2005
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