Electronics and Telecommunication Engineering - Vishwakarma ...

Bansilal Ramnath Agarwal Charitable Trust’s
Vishwakarma Institute of Technology, Pune – 411 037
Department of Electronics and Telecommunication Engineering
B. Cascode amplifier.
Unit IV: Datapath and Memory Design
(8 Hrs)
A. Adder- Single bit adder, bit parallel adder, carry save adder, carry-look ahead adder,
carry select adder, transmission adder, Parity generator, comparators, Multipliers- Array
multiplier, Radix n-multiplier, Wallace tree multiplier, serial multiplier, Shifters-Barrel
shifter, logarithmic shifter, Synchronizers and Arbiters, CMOS Memories-classification
of memories, Memory architecture, read only memories, Nonvolatile read write
memories, Read write memories, memory peripheral circuits.
B. Manchester carry Adder, Booth’s Multiplier.
Unit V: Fabrication and Layout
(8 Hrs)
A. Basic CMOS fabrication flow, front end and back end fabrication steps, Self aligned
CMOS process, N well, P well, Twin tub, Design rules, Layout of CMOS Inverter,
Verification of Layout.
B. NMOS Technology
Text Books
1. Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall India.
2. CMOS analog circuit Design, P.E. Allen and D.r. Holberg, second Edition, Oxford.
3. VLSI Technology, S.M.Sze, TMH.
Reference Books
1. “Principles of CMOS VLSI Design”, N. Weste and K. Eshranghian, Addison
Wesley.
2. “CMOS”, RJ Baker, Wiley IEEE Press, 2004.
Structure & Syllabus of B.E (E&TC) Program – Pattern ‘C11’, Rev01, dt. 2/4/2011
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