Electronics and Telecommunication Engineering - Vishwakarma ...

Bansilal Ramnath Agarwal Charitable Trust’s
Vishwakarma Institute of Technology, Pune – 411 037
Department of Electronics and Telecommunication Engineering
FF No.: 654
EC30107 :: DIGITAL INTREGRATED CIRCUITS
Credits: 03
Teaching Scheme: - Theory 3 Hrs/Week
Prerequisites: Nil
Objectives:
• To study behavior of CMOS inverter in detail.
• To draw NAND, NOR, XOR gates using CMOS logic.
• To study VHDL as EDA Tool.
• Mapping with PEOs:2,35,6,7,8
Unit I: Introduction to HDL
(8 Hr)
A. What is HDL, VHDL, role of hardware description languages, motivation. Describing
Hardware in VHDL- data types, data objects data operators, Event and transactions,
attributes. Concurrency, Entity, Architecture, concurrent Signal assignments, resolved
signals, conditional signal assignment statement, selected signal assignment statement,
constructing VHDL models.
Delays- Inertial Delay, transport delay, Delta delay, waveform and timing.
B. predefined attributes.
Unit II: Modeling in VHDL
(8 Hr)
A. Behavior Modeling- Process construct, programming constructs-If –then else
statements, case statement, loop statements, more on process, wait statement, using signal
in process, state machine modeling. Structural modeling, component declaration,
instantiation, Generics, configuration and binding.
B. Generate statement.
Unit III: Advanced Topics
(7 Hr)
A. Sub-programs and overloading -Functions, Procedures. Packages and libraries. Basic
principles of Synthesis,. Test benches-test bench for combinational and test bench for
sequential circuits.
B. Synthesizable and non-synthesizable statements.
Structure & Syllabus of B.E (E&TC) Program – Pattern ‘C11’, Rev01, dt. 2/4/2011
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