SEMATECH Advanced Technology

SEMATECH / ISMI Symposium
Taiwan 2008
Accelerating the next technology revolution
SEMATECH Advanced Technology
John Warlaumont
VP, Advanced Technology
Albany Senior Site Executive
9 December 2008
Copyright ©2008
SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center
and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

SEMATECH delivers unique value to
its members and partners
• Leading-edge technology development and
in-depth technical expertise
– Foundation for industry’s major break-throughs
• Focus on real-world manufacturability and
cost of ownership
• Fab and equipment productivity
• Rapid processing and prototyping
• Industry leadership and coordination
• High leverage, high return on investment
2 December 2008 2

Major technology changes –
innovation required
DRAM half-pitch /
logic generation
45nm 32nm 22nm – 16nm
ITRS 2010 2012 2014 - 2016
Leading edge companies 2008 2010 2012 - 2014
Most likely technology (potential first introduction)
Lithography
193nm
193i /
193nm
193i (NA
~1.3)
EUV / double patterning 193i
FEP
Planar (HKMG, strain)
Planar / non-planar (2 nd Gen
HKMG, strain, high mobility
channels..)
Interconnect Cu / low-k Cu / low-k / 3D
Wafer Size 300mm 300mm / 450mm
2 December 2008 3 3

Technology innovation and
manufacturing productivity
Technology Challenges
Increase
transistors
per area
• Lithography
• Metrology
• Devices
• Design
• 3D Interconnects
Decrease cost per function
Productivity Challenges
Cost per
wafer
Increase good
wafer output
Reduce
operating cost
Cost per
area
Area per
wafer
Wafer size
conversion
2 December 2008 4 4

Broad strategy for high return
• Extend current technologies to their limits
• Build infrastructure for emerging technologies
• Evaluate and narrow future options
Lithography – more Moore
• 193nm Immersion
• EUV
• Mask
• Alternative Lithography
Interconnect – more than Moore
• 3D TSV Interconnects
Metrology – current and future Moore
2 December 2008 5

Lithography roadmap
45 nm HP
HVM
193i (water)
Blue – SMT focus
32 nm HP
DEV
HVM
193i Double patterning
EUVL (late insertions)
193i (High index)
22 nm HP
DEV
HVM
EUVL
193i Double exposure, DP/HI
Nanoimprint, Maskless
16 nm HP
SEMATECH RoadmapITRS Roadmap
DEV
HVM
EUVL (High NA)
Nanoimprint,
Maskless,
Self-assembly?
12 nm HP
2010
2013 2016 2019 2022
HVM
High Volume Manufacturing (ITRS)
2 December 2008 6

Beyond 2008: SEMATECH vision
• EUVL
– Deliver key capability to enable EUV mask blanks at ≤22nm HP
– Enable resist development at ≤22nm HP
• Provide imaging capabilities
– Find methods to reduce source cost-of-ownership
– Drive defect free reticle carriers to commercialization
• 193i
– Push materials to the limit of extending immersion litho
• Mask
– Provide mask infrastructure capability to keep masks cost-effective (Both
EUVL and 193i)
– Provide key mask tools needed to enable future litho technologies
• Alternative Litho
– Demonstrate that nanoimprint can provide semiconductor-quality
lithography
– Monitor maskless solutions for wafer printing
2 December 2008 7

Lithography portfolio at a glance
2 December 2008 8

SEMATCH EUV imaging capabilities
• LBNL MET
– 0.3 NA, small field, synchrotron source
– Located at Lawrence Berkeley National Laboratory
• LBNL AIT
– 0.35NA, aerial-imaging, synchrotron source
– Located at Lawrence Berkeley National Laboratory
• Albany eMET
– 0.3 NA, small field, xenon plasma source
– Located at SEMATECH-Albany
• Albany ADT
– ASML alpha tool
– 0.25 NA, full field, tin plasma source
– Located in Albany 300mm facility
– Shared use with Albany partners
2 December 2008 9

EUV highlight: demonstrated sub 32 nm
hp in EUV resists with LBNL MET
24nm HP
Mag. 500K
45
32nm HVM Spec.
LBNL MET
40 0.3NA, Rot. Dipole
Mag. 500K Mag. 500K
35
ADT/PPT
Mag. 500K
30
0.25NA,
22nm HP
Conv.
25
20
15
Mag. 500K
10
20nm HP
5
0
30nm CH Mag. 500K
Resolution LWR SensitivityResist Collapse
@ T pr
50nm
32nm HP 1.7nm 10mJ/cm 2 AR 2.5 (T pr
80nm)
22nm HP 1.2nm 10mJ/cm 2 AR 2.5 (T pr
55nm)
Target Specification
A
B
C
D
E
F
G
• Resolution:
– 20 nm 1:1 L/S
– 30 nm 1:1 C/H
• Sensitivity:
– L/S ~ 15 mJ/cm 2
– C/H ~ 50 mJ/cm 2
• Line Edge
Roughness:
– L/S ~ 4-5 nm
– C/H ~ TBD
2 December 2008 10

SEMATECH zone plate system (AIT)
enables 32 – 27 nm hp aerial imaging
• Recent improvements in resolution and
contrast
150 nm lines
2007
2008 2008
↑NA
• SEMATECH actinic
imaging tool (AIT) sees
defect details not
detected by the best
visible light inspection
tool (M7360)
• Unique one-of-a-kind tool
AIT
• Available for SEMATECH member use
• Commercial tool in plan ~ 3 years away
M7360
2 December 2008 11

Accelerating the mask-defect-litho
learning cycle: only accessible through
SEMATECH
Defect-free
Mask Blanks
SEMATECH Defect Inspection Tools
Programmed Mask Defects
Resist Image Aerial Image
SEMATECH MET’s
SEMATECH AIT
100 nm
2 µm
SEMATECH
Berkeley MET
SEMATECH
Albany MET
Mask imaging: 100
nm Resolution
2 December 2008 12

Mask inspection roadmap
70
60
RFI Funding Dock/UTP
Tool Development
Defect Sensitivity (nm)
50
40
30
20
Multilayer
M7360
Substrate
M7360
Upgrade
Limit of M7360
Platform
Actinic Tool Development Time
2.5G Optical
Based System
3.0G Actinic
Based
10
RFI Dock JDA/UTP
2.5G
Upgrade
0
Q3'11
Q1'11
Q3'10
Q1'10
Q3'09
Q1'09
Q3'08
Q1'08
2 December 2008 13

Pit smoothing by cleaning
After smooth/clean
After cleaning –
2x reduction
Before smoothing After smoothing – 2x reduction After ML deposition
SEMATECH has developed new cleaning processes
demonstrating reduction in pit depth distribution
2 December 2008 14

Mask blank reduction pilot line
Targeting manufacturing-grade defect level
Total defect density on ML coated mask blank
scaled to 18nm sensitivity (cm-2)
1000
100
0.1
SEMATECH Mask Blank Defect Reduction Progress
10
1
MBDC
Pilot Line Goal
Pilot Line
Champion
Median
0.01
Jan-04 Jan-05 Jan-06 Jan-07 Jan-08 Jan-09 Jan-10 Jan-11
2 December 2008 15

Building EUV manufacturability:
EUV reticle handling
• Orders of magnitude improvement made over last three
years
• Essentially zero defects added during use
80
Average Adders
70
60
50
40
30
20
Industry data at 2005
SEMATECH data at 2008
42
14
56
sPod carrier used in 2008
10
0
0.1 0.01 0.11
Shipping
Vacuum
Total
Inspection area (142x142mm) and 53 nm sensitivity
With inner pod exposed
2 December 2008 16

Immersion program 2008 highlights
• Lutetium Aluminum Garnet absorption improved from
0.11/cm to 0.025/cm
• Immersion fluids made with nanoparticles:
– HfO2 Nanoparticles with 1 nm diameter synthesized
– G3 nanofluid feasibility shown
• World’s first LuAG imaging at 32nm and 30 nm hp
Aqueous Immersion
Fluid
Volume (%)
16
14
12
10
8
6
4
2
0
D H
= 1nm
-2
0.1 1 10 100 1000 10000
D H
(nm)
70 wt%, 19 vol %
R.I.= 1.442 @ 589 nm, ~1.6
@ 193nm
Organic Immersion
Fluid
5 vol %
R.I. = 1.495 @ 589
nm,
~1.7 @ 193nm
32nm LuAG Imaging
LuAG absorbance
improved
Old
Ne
w
2 December 2008 17

Alternative litho program 2008 highlights
• Molecular imprints Imprio 300
• Factory acceptance testing achieved 23nm
mean+3sigma mix-and-match overlay
• Installation at SEMATECH-Albany completed
Imprio300
NanoImprint Image;
30nm
2 December 2008 18

SEMATECH 3D program - moving
beyond low-k materials limits
4.5
4
3.5
k Effective
3
2.5
ITRS hp65
ITRS hp45
ITRS hp32
2
1.5
Historical
performance, k eff
Potential
impact, 3D*
1
1990 1995 2000 2005 2010 2015 2020
2 December 2008 19

Driving a strategy for 3D
implementation
Option Assessment
• Material
• Via Formation
• Bonding
• Integration
Option Narrowing
• Cost Modeling
• Performance
Evaluations
• Risk Assessments
• Product Requirements
• Tool Benchmarking
• Process Benchmarking
Technology
Development
• Materials
• UPD & Integration
• Equipment Hardening
• Device Impact
• Early Reliability
• Cost Modeling
Manufacturing
Solution
• Test bed for new
integration concepts
Phase 1 (2005-2007)
Equipment demos, 200mm integration,
risk assessments
Phase 2 (2008-2009)
State of the art, 300mm 3D equipment
and integration
2 December 2008 20

SEMATECH 3D R&D center
300mm CNSE facility
State of the art
300mm
3D tools
SEMATECH 3D R&D/prototyping center
Materials characterization
Unit process development
Tool development/hardening
Integration (WtW & DtW)
Yield
Early reliability
Fab/assembly overlap region
Product interlock
Impact on CMOS performance
Layout rules
Test methodology
Roadmaps
Standards
Cost models
2 December 2008 21

3D options
• Die to die stacking
• Die to wafer
Through Silicon Vias
SEMATECH R&D
• Wafer to wafer
Courtesy: Samsung.
Courtesy: Tezzaron
• Device level
K Saraswat Stanford U.
2 December 2008 22

Benefits of 3D ICs with TSVs
• Improved form factor
– Can provide smaller footprint and/or increased density
– Can result in higher yield
• High functionality
– Improved integration of heterogeneous technologies, materials and signals over SoC
• High performance
– High bandwidth with shorter wires (lower RC)
• Lower power consumption
– Shorter wires and lower overall I/O count
• Cost
– Addresses slowdown in productivity gain (from scaling)
– Optimizes cost structure for each “level” in 3D stack
– Short time to market for products
Through Silicon Vias (TSVs) have the potential to combine all these
advantages
SEMATECH’s 3D program will deliver process technology solutions for
high volume TSV manufacturing
2 December 2008 23

SEMATECH roadmap
• SEMATECH roadmap target is
1 year before ITRS
• R&D work (i.e. early materials
and tool development) would
start 4-5 years ahead of ITRS
roadmap
• R&D starting now would target
product volume in 2011 – 2013
• Process ready and
feasibility demonstrated in
SEMATECH by 2009/2010
Half Pitch 65 45 32 22
ITRS 2007 2010 2013 2016
SEMATECH 2006 2009 2012 2015
Early dev
tools/Materials
HD TSV
diameter (µm)
HD minimum
pitch (µm)
2004 2005-
2007
1.6-
2.5
1.1-
1.7
2007-
2010
0.7-
1.1
2010-
2013
0.5-
0.9
5 3.8 2 1.7
TSV layer
thickness
50 15 10 10
2 December 2008 24

3D program elements
Equipment/process evaluation 3D module integration / reliability Product impact/value
Equipment
Qualification
& Readiness
- Specs
- Uniformity
- Particles
- Cp, Cpk
Materials &
Process
Development
- Evaluation of
properties
- Basic UPD
- TSV RIE
- Via fill
- Bond materials
Bonding &
Thinning
Development
- Process
development
- Ultrathin (

SEMATECH’s wafer cost model
Process :
Cost of consumables,
throughput
Yield
Tool :
Cost, depreciation,
maintenance
down time, footprint
Integration:
Number of levels,
process flow
Wafer Cost
Model
Process costs
per step
Wafer starts
dependence
Yield costs
# Tools required
2 December 2008 26

WCM example: TSV fabrication
TSV Cost per Wafer vs # Vias/die
10000
1000
100
Laser-A
Laser-B
Laser-C
Laser-D
DRIE-A
DRIE-B
DRIE-C
DRIE-D
Laser
Etch
Laser is cost effective
Etch is cost effective
10
10 100 1000 10000
# Vias / die
2 December 2008 27

SEMATECH metrology
Critical enabler of R&D and manufacturing
University-based
Research Programs
Joint Activities
with NIST
Advanced Metrology
Techniques
Development
Metrology for High
Productivity
Manufacturing
Joint ISMI Activities
in Albany
• Lab tools
• Alpha tools
• Beta tools
• Early user fab tools
• Technique development
• Tool development associate
members
• Fab tools
• Benchmarking evaluations
• BKM development
2 December 2008 28

ITRS metrology potential solutions for
22 nm node
2007, 2010, 2013, 2016,
65 nm 45 nm 32 nm 22 nm
Lithography (Wafer Level)
CD-SEM
Scatterometry
Scatterometry on track
CD_SAXS
CD-SPM
Innovative Methods
Destructive ion beam
Research Required
Lithography (M ask Level)
Lithography (Overlay)
Environmental SEM
Innovative Method
SPM
Optical methods
SEM
Development Underway
Qualification/Pre-production
Continuous Improvement
Scattering based optical
FEP
O ptical and x-ray film thickness
Stress Metrology
Compositional Metrology
Interconnect
Optical, x-ray and acoustic film thickness
Stress metrology
In-situ sensors for CMP
2 December 2008 29

SEMATECH metrology program
• Litho Metrology
– CD and overlay technology systems
– Member sharing of best practices
• Defect Metrology
– Defect detection and yield learning
– Standards and tool improvement
– Models to extend current systems
• Films Metrology
– Film thickness, composition, stress, electrical performance
• Manufacturing productivity improvement
2 December 2008 30

SEMATECH optical metrology
innovation program
• Background
– When thin films approach the nanometer scale, variations in
thickness, composition, stress, and defects influence the optical
properties
– Spectroscopic ellipsometry and polarized reflectivity are highly
sensitive to these variations
– Optical properties highly sensitive to thickness, composition, stress
• Tools: KLA-Aleris
• Program elements
– Develop new optical measurements and models for
high-k and metal gate films
– Develop optical measurements of stress in advanced
channel layers
– Enable scatterometry measurements of Fin arrays
through improved data interpretation software
2 December 2008 31

TEM-EELS-FIB suite
• Background
– TEM with Electron Energy Loss Spectroscopy (EELS)
– Leading candidate to replace SEM based EDX for inline elemental analysis
of defects for the 45nm node and below
– The major limitation of S/TEM/EELS is low throughput, which this program
addresses
• Tools
– FEI Titan high resolution transmission electron microscope
with electron energy loss spectrometer
– CLM3D dual beam-focused ion bean specimen prep
– TL150 specimen handling system
• Key program elements
– Improve throughput of lamella extraction process
– Development of S/TEM EDX and EELS strategies
for fast defect sourcing
– TEM image magnification calibration based upon
known lattice
– Electron tomography capability and improvement
2 December 2008 32

Evolving SEMATECH model
• More resources
– Additional partners, increased financial leverage
• More facilities
– Increased access to fab/processing facilities
• More flexibility
– New programs, new participation options
• Same goal
– Drive technology innovation and manufacturing
productivity
– Moore, more Moore, some more than Moore
2 December 2008 33

SEMATECH – membership flexibility
• New participation options
– SEMATECH membership – all programs
– ISMI membership – manufacturing programs
– Program memberships – 3D, memory, metrology, mask infrastructure, resist
• New supplier engagements
– Joint Development Agreements
– Resist Test and Mask Blank Development Centers
• Private access - supplier owns IP
– Associate memberships
• Partial access to existing SEMATECH program
• SEMATECH research aligned with associate members’ early product
development needs
• 2008 memberships (publicly announced):
– TEL – 3D program
– Accretech – 3D program
– Rudolph – Metrology program
2 December 2008 34

SEMATECH has facilities and access
to capabilities and experts worldwide
Texas
• Front End
Processes
• ISMI
• ATDF wafer
processing
Universities
• Over 60
universities in
U.S., Asia, Europe
and Australia
Albany, NY
• Lithography
– EUV
– Immersion
• 3D TSVs
• CSR wafer
processing
National Labs
• Advanced
metrology
• EUV
exposure
2 December 2008 35

Collaboration of SEMATECH / NY in
Albany
NanoFab 300S
32K ft2 Cleanroom
NanoFab 300N
35K Cleanroom
NanoFab 300C
15K ft2 Cleanroom
NanoFab 300E
NanoFab 200
4K Cleanroom
750K ft 2 cutting-edge facilities (80,000 ft 2 300mm Wafer Cleanrooms)
2 December 2008 36

Albany 300mm piloting facility
• Shared use by NY partners
– Separate programs, single
facility
• IBM / CNSE CSR program
• SEMATECH / CNSE
program
• Designed for 32nm node
and beyond but compatible
with previous generations
– Unit process, module
integration, full flow capability
2 December 2008 37

Accelerating the next technology revolution
Thank you
Copyright ©2008
SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center
and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.