RAiO RA8806 - Display Future
RAiO RA8806 - Display Future
RAiO RA8806 - Display Future
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Version 1.3<br />
<strong>RA8806</strong><br />
Two Layers Character/Graphic LCD Controller<br />
<strong>RA8806</strong><br />
<strong>Display</strong><br />
Data RAM<br />
Memory-Write<br />
LCD-Scan<br />
MCU<br />
Interface<br />
Controller<br />
LCD<br />
Driver<br />
Figure 6-34 : Data Flow of DDRAM<br />
XCLK<br />
LP<br />
ITCR<br />
COM_SCAN<br />
T_COM<br />
Figure 6-35 : Scan for Each COM Line<br />
Memory Write Busy:<br />
Following two conditions will cause the Memory write busy:<br />
1. When MPU write data in text-mode. Depending on different size of font, it needs an enough<br />
time to write the font to DDRAM. At the period, <strong>RA8806</strong> can’t access the DDRAM again, it’s<br />
a memory write busy condition.<br />
2. When MPU program <strong>RA8806</strong> as a memory clear function(FNCR Bit-3 = 1). The period of<br />
clear DDRAM also cause a memory write busy.<br />
It will cause the DDRAM lost when accessing DDRAM in the period of Memory Write Busy. So user<br />
must check the busy status after the upper two conditions is done.<br />
Besides, <strong>RA8806</strong> provide polarity setting for “BUSY” and interrupt “INT” pin. (Please refer to register<br />
MISC)<br />
Normally, this “BUSY” pin is connected to MPU I/O input, and then MPU have to monitor this pin<br />
before accessing <strong>RA8806</strong>. The following is the timing of BUSY pin. The BUSY can be active high or<br />
low that depend on the setting of REG[01h] Bit-5.<br />
<strong>RAiO</strong> TECHNOLOGY INC. 66/193 www.raio.com.tw
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