RAiO RA8806 - Display Future
RAiO RA8806 - Display Future
RAiO RA8806 - Display Future
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Version 1.3<br />
<strong>RA8806</strong><br />
Two Layers Character/Graphic LCD Controller<br />
EIO1<br />
160-channel<br />
(Common)<br />
Y1~Y160<br />
VDD<br />
VSS<br />
MD<br />
S/C<br />
L/R<br />
DI0~DI7<br />
FR<br />
LP<br />
DISPOFF<br />
XCK<br />
160*160 Dot<br />
LCD Panel<br />
EIO2<br />
<strong>RA8806</strong><br />
YD<br />
Y1~Y160<br />
FR<br />
LP<br />
ZDOFF<br />
XCK<br />
LD[7:0]<br />
XCK<br />
EIO2<br />
DISPOFF<br />
DI0~DI7<br />
LP<br />
L/R<br />
FR<br />
160-channel<br />
(Segment)<br />
S/C<br />
MD<br />
EIO1<br />
Figure 6-11 : Application Circuit Diagram for 160x160 Panel<br />
Table 6-4 is the <strong>RA8806</strong> driver signals mapping to different driver ICs’ pin names. Note, do not need<br />
add any capacitor on these for LCD driver signals. If add external capacitor on these pins to<br />
ground or VDD, then the maximum limitation is 30pF.<br />
Table 6-4 : Driver IC I/F Name vs. <strong>RA8806</strong><br />
<strong>RA8806</strong><br />
Driver I/F<br />
Driver IC I/F Name<br />
Definition of Driver IC I/F<br />
LP<br />
LP<br />
Data Latch Clock<br />
Latch Pulse in one line<br />
LOAD Latch pulse of display data<br />
CL1<br />
Data Latch Pulse<br />
CP<br />
Data Shift Clock<br />
Clock pulse for segment shift register<br />
XCK<br />
SCP<br />
Shift Clock Pulse for X-Drivers<br />
CL2<br />
Data Shift Pulse<br />
HSCP Shift Clock Pulse<br />
FLM<br />
Scan Start-up Signal<br />
First Line Marker<br />
FR<br />
Frame Pulse<br />
YD<br />
Frame start signal(First line mark of common<br />
FRAME<br />
signal)<br />
CDATA Synchronous Data<br />
FR<br />
DF(M)<br />
Switch signal to convert LCD drive waveform<br />
into AC<br />
LD[7:0] D[7:0] LCD Data Bus<br />
/DISPOFF <strong>Display</strong> OFF<br />
ZDOFF<br />
/D.OFF <strong>Display</strong> OFF<br />
DISP<br />
<strong>Display</strong> OFF<br />
<strong>RAiO</strong> TECHNOLOGY INC. 34/193 www.raio.com.tw
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