40nm...40 Nanometer - UMC

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DFM Methodology UMC offers optimal DFM (Design For Manufacturability) solutions to effectively and efficiently address factors that may negatively affect yield and performance for advanced technology designs. UMC’s DFM solutions include advanced process models incorporated in SPICE and extraction decks for predicting random and systematic variations, technology files, DFM-compliant libraries and IP that embrace the intricacies of the fabrication process. Concise DFM recommendation rules are available along with a comprehensive rule-deck runset strategy to fulfill various design requirements. DFM Methodology Roadmap Restricted Rules Statistical Timing Analysis Critical Area Analysis Modeling with CMP Effects Litho Simulation Checks Modeling with LOD & WPE Monte Carlo Models Modeling with WEE UMC also offers pre-tapeout Optical Proximity Correction (OPC) and Litho Rule DFM Rules Check (LRC) for custom designs in addition to our standard post-tapeout services that include OPC, Litho Simulation Check (LSC), dummy fill, and metal slotting. At 65nm and below, UMC offers a DFM Design 0.13um 90nm 65nm 40nm Enablement Kit (DEK) to seamlessly support model-based DFM tools. The DEK has a built-in Graphic User Interface (GUI) for DFM design database setup, and is completed with application notes and qualification reports for design reference. UMC e-Fuse Features To reduce chip area, achieve better reliability performance, and shorten repair time compared to conventional Al fuse, UMC has developed an e-fuse solution to target the needs of a broad range of applications. The fuse array and complete functional macro are offered to ease the integration process for customers. Both wafer level and package level fuse are supported. Moreover, customers can use e-fuse for the OTP (one time programming) function to save overall costs. Logic Compatible Complete Functional IP Macros Design-Friendly Features Flexibility • No extra masks necessary • Only one extra pad required • Fuse array, programming circuit, sensing amplifier • Serial and parallel architecture • Allows metal routing over fuses (M6 and above) • Programmable at package level • Wafer level fuse options • Package level fuse options
Virtual Inductor Library UMC has worked with its EDA tool partners to deliver the industry's first parameterized inductor design kit based on full-wave simulation: the Virtual Inductor Library (VIL). The VIL enables RFCMOS designers to create and simulate custom inductor geometries that are compatible with UMC's processes. It is built upon UMC's Electromagnetic Design Methodology (EMDM), which allows engineers to easily and accurately create any RF structure. EMDM gives designers the flexibility to innovate new geometries simply by editing parameters such as diameter, number of turns or width. Spiral Differential w/o center tap Differential with center tap The GUI based VIL can be used to simulate all types of RF inductors. Stack Virtual Capacitor Library UMC and its EDA tool partners have delivered the industry's first parameterized MOM capacitor design kit based on full-wave simulation: the Virtual Capacitor Library (VCL). The VCL enables RFCMOS designers to create and simulate custom capacitor geometries that are compatible with UMC's processes. It is built upon UMC's Electromagnetic Design Methodology (EMDM), which allows engineers to easily and accurately create any RF structure. EMDM gives designers the flexibility to innovate new geometries simply by editing parameters such as number of metal and fingers, arrays, and length of fingers for capacitor. The GUI based VCL can be used to simulate all types of RF capacitors.
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Page 3 and 4: 40nm Logic/MS/RF Devices 40nm Logic
Page 5 and 6: Low Power Features of Standard Cell
Page 7: Reference Design Flow and Vendor Su
Page 11 and 12: Optimum Inductor Finder (OIF) UMC o

40nm...40 Nanometer - UMC

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