40nm...40 Nanometer - UMC

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Fundamental IP Support Fundamental IPs (standard cells, I/Os, and memory compilers listed below) are optimized to UMC technologies, and are planned for development from several leading vendors to be available free-of-charge (please contact a UMC account manager for more information). Customers can also leverage application specific IPs for DTV, graphics, networking, etc. IPs available through UMC are DFM (Design for Manufacturing) compliant for better manufacturability. Process Node G 40nm LP Ultra-LVT - Þ Standard Cell Library LVT Þ Þ RVT Þ Þ HVT Þ Þ I/O Library 2.5V *(2) Þ Þ Single Port SRAM Compiler Þ Þ Dual Port SRAM Compiler Þ Þ Single Port Register File Þ Þ Dual Port Register File Þ Þ ROM Compiler Þ Þ *(1) The listed IPs are planned for 40nm development. For the most updated information, please contact your account manager. *(2) 1.8V/2.5V/3.3V multi-voltage I/O library Interface/Functional IP Support ITEM Feature Vandor 40nm LP USB 2.0 pico PHY Synopsys Þ USB 3.0 5Gb/s Synopsys Þ PCIE Gen II Synopsys Þ SATA3 6G Synopsys Þ DDR multi PHY DDR2, 3, 3L, mDDR, LPDDR2 PHY(1066) Synopsys Þ DDR 3/2 1600MHz Synopsys Þ HDMI 1.4a TX & HEAC Synopsys Þ OTP 8Kb~4Mb Kilopass Þ MIPI D PHY TX & RX Synopsys Þ PLL Input frequency range:25~66MHz, Output frequency range:200~400MHz FTC Þ PLL Input frequency range:20~200MHz, Output frequency range:500~ 1000MHz FTC Þ *For more information, please contact your account manager.
Low Power Features of Standard Cell Library With today's proliferation of low power applications, lowering energy consumption without sacrificing performance has become a critical concern for designers of power management chips for portable electronics. UMC supports its standard cell library with low power design features, including multiple Vt, clock-gating, level shifter and other features to complement UMC’s complete low power solution. Operating Power Type Voltage Island & Scaling Clock Gating & Frequency Scaling Support Features Level Shifters w / Insulator Power & Timing Model @ 80% of Vdd Support 40nm 65nm 90nm 0.13um Þ Þ Þ Þ Clock Gated F/F Þ Þ Þ Þ Multi-Vt Multi-Vt cells Þ Þ Þ Þ Leakage Power Power Gating Isolation cells, Retention F/F Headers / Footers, etc. Þ Þ Þ Þ Body Bias Tapless cells Timing / Power Model Þ Þ Þ Þ
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40nm...40 Nanometer - UMC

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