Vishwakarma Institute of Technology B.E. (Electronics)

Bansilal Ramnath Agarwal Charitable Trust’s
Vishwakarma Institute of Technology, Pune – 411 037
Department of Electronics Engineering
FF No. : 654
EC42105:: VLSI DESIGN
Credits: 03
Teaching Scheme: - Theory 3 Hrs/Week
Prerequisites: Nil
Objectives:
-To study concepts of CMOS Analog & Digital Design.
- To be familiar with CMOS fabrication process.
Mapping with PEO :2,3,5,6,7,8,9
Unit I: MOSFET SPICE modeling
(8 Hrs)
A] Modeling of semiconductor devices, MOSFET modeling, small signal model for
MOS transistor, Modeling of secondary & short channel effects, sub threshold modeling,
understanding role of parameters in model, Introduction to industry standard models
like PSP, Bsim.
B] Surface potential and threshold voltage based model.
Unit II: Analog CMOS sub-circuits
(8 Hrs)
A] MOS Switch, Calculation of charge feed through error, MOS diode, Current Sink and
Sources, Designing cascade current sink for a given V min, Designing the self biased high
swing cascade current sink for a given V min, Current Mirrors, Aspect ratio errors in
current amplifiers, Reduction of the aspect ratio error in current amplifier, Current and
voltage references, Bandgap reference.
B] Design of a Bandgap voltage reference.
Unit III: CMOS Amplifiers
(8 Hrs)
A] CMOS Amplifiers, Inverters, Active load Inverter, Current Source Inverter, Push pull
inverter, Noise analysis of inverter, Differential amplifier, Large Signal analysis,
Calculation of the worst case input common mode range of the N channel input
differential amplifier, Small signal analysis of differential amplifier, Slew rate and noise,
Structure & Syllabus of B.E (Electronics ) Program – Pattern ‘C11’, Rev01, dt. 2/4/2011
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