Vishwakarma Institute of Technology B.E. (Electronics)

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Bansilal Ramnath Agarwal Charitable Trust’s Vishwakarma Institute of Technology, Pune – 411 037 Department of Electronics Engineering FF No. : 654 EC30107 :: DIGITAL INTREGRATED CIRCUITS Credits: 03 Teaching Scheme: - Theory 3 Hrs/Week Prerequisites: Nil Objectives: - To study behavior of CMOS inverter in detail. - To draw NAND, NOR, XOR gates using CMOS logic. - To study VHDL as EDA Tool. - Mapping with PEO :2,3,4,5,6,7,8 Unit I : Introduction to HDL (8 Hr) A] What is HDL, VHDL, role of hardware description languages, motivation. Describing Hardware in VHDL- data types, data objects data operators, Event and transactions, attributes. Concurrency, Entity, Architecture, concurrent Signal assignments, resolved signals, conditional signal assignment statement, selected signal assignment statement, constructing VHDL models. Delays- Inertial Delay, transport delay, Delta delay, waveform and timing. B] predefined attributes. Unit II: Modeling in VHDL (8 Hr) A] Behavior Modeling- Process construct, programming constructs-If –then else statements, case statement, loop statements, more on process, wait statement, using signal in process, state machine modeling. Structural modeling, component declaration, instantiation, Generics, configuration and binding. B] Generate statement. Unit III: Advanced Topics (7 Hr) A] Sub-programs and overloading -Functions, Procedures. Packages and libraries. Basic principles of Synthesis,. Test benches-test bench for combinational and test bench for sequential circuits. B] Synthesizable and non-synthesizable statements. Structure & Syllabus of B.E (Electronics ) Program – Pattern ‘C11’, Rev01, dt. 2/4/2011 28
Bansilal Ramnath Agarwal Charitable Trust’s Vishwakarma Institute of Technology, Pune – 411 037 Department of Electronics Engineering Unit IV: Static CMOS (8 Hr) A] Recap of I-V characteristics for MOS , CMOS inverter, VTC, detail analysis of VTC, noise Margin, Regenerative property, performance, Power and energy consumption, Power consumption and Power delay product, CMOS logic design, Transmission gate, Ratioed logic, Pass transistor logic, power consumption in CMOS. B] Resistive MOS Inverter. Unit V: Dynamic CMOS design (9 Hr) A] Dynamic logic –basic principles, Domino logic, Zipper CMOS, DCVSL logic, CMOS Sequential circuit Design- CMOS flip-flops, dynamic sequential circuits- Pseudo static Latch, C2MOS Latch, NORA CMOS, TSPCL, Non-Bistable. B] Two phase Flip-flop, schmitt trigger Text Books 1. “Digital Integrated Circuits: A Design Perspective”, J. Rabaey, Prentice Hall India, 1997. 2. “ VHDL Primer”, J Bhaskar , Addison Wesley Longman, 2000. Reference Books 1. “Principles of CMOS VLSI Design”, N. Weste and K. Eshranghian, Addison Wesley. 2.”CMOS Digital Integrated Circuits”, Kang S. M.,TMH, 3rd edition, 2003. 3. “VHDL”, D. Perry, 2nd Ed., McGraw Hill International, 1995. 4. “Introductory VHDL from simulation to synthesis”Sudhakar Yalamanchili, , Pearson education. Structure & Syllabus of B.E (Electronics ) Program – Pattern ‘C11’, Rev01, dt. 2/4/2011 29
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Vishwakarma Institute of Technology B.E. (Electronics)

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