MMC2107 - Freescale Semiconductor

Electrical Specifications
Freescale Semiconductor, Inc.
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Freescale Semiconductor, I
22.8 PLL Electrical Specifications
Table 22-5. PLL Electrical Specifications
(V DD and V DDSYN = 2.7 to 3.6 V, V SS = V SSSYN = 0 V, T A = T L to T H )
PLL reference frequency range
Crystal reference
External reference
1:1 mode
System frequency (1)
External reference
On-chip PLL frequency
Parameter Symbol Min Max Unit
f ref
2
2
10
f sys 0
f ref /64
Loss of reference frequency (2) f LOR 100 250 kHz
Self-clocked mode frequency (3) f SCM 0.5 15 MHz
EXTAL input high voltage
Crystal mode
All other modes (1:1, bypass, external)
EXTAL input low voltage
Crystal mode
All other modes (1:1, bypass, external)
V IHEXT V DDSYN –1.0
2.0
V ILEXT
10.0
33.0
33.0
33.0
33.0
V DDSYN
V DDSYN
V SSSYN 1.0
V SSSYN 0.8
PLL lock time (4), (5) t LPLL — 200 µs
Powerup-to-lock Time (4), (5)
Without crystal reference
t LPLK — 200 µs
1:1 clock skew (between CLKOUT and EXTAL) (6) t Skew –2 2 ns
Duty cycle of reference (4) t dc 40 60 % f sys
Frequency un-LOCK range f UL –1.5 1.5 % f sys
Frequency LOCK range f LCK –0.75 0.75 % f sys
CLKOUT period jitter (7)
Measured at f sys maximum
Peak-to-peak jitter (clock edge to clock edge)
Long-term jitter (averaged over 2-ms interval)
C Jitter
—
—
5
0.01
MHz
MHz
V
V
% f sys
1. All internal registers retain data at 0 Hz.
2. Loss of reference frequency is the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
3. Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f LOR with
default MFD/RFD settings.
4. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
5. Assuming a reference is available at power-up, lock time is measured from the time V DD and V DDSYN are valid to RSTOUT
negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal startup time must be added to
the PLL lock time to determine the total startup time.
6. PLL is operating in 1:1 PLL mode.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys .
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V DDSYN and V SSSYN and variation in crystal oscillator frequency increase the C Jitter
percentage for a given interval.
Technical Data MMC2107 – Rev. 2.0
590 Electrical Specifications MOTOROLA
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