MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
21.14.8.2 Trace Operation
To initiate trace mode operation:
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Freescale Semiconductor, I
1. Load the OTC register with a value. This value must be non-zero,
unless sequential breakpoint control operation is enabled in the
OCR register. In this case, a value of zero (indicating a single
instruction) is allowed.
2. Initialize the program counter and instruction register in the
CPUSCR with values corresponding to the start location of the
instruction(s) to be executed real-time.
3. Set the TME bit in the OCR.
21.14.9 Methods of Entering Debug Mode
4. Release the processor from debug mode by executing the
appropriate command issued by the external command controller.
When debug mode is exited, the counter is decremented after each
execution of an instruction. Interrupts can be serviced, and all
instructions executed (including interrupt services) will decrement the
trace counter.
When the trace counter decrements to zero, the OnCE control logic
requests that the processor re-enter debug mode, and the trace
occurrence bit TO in the OSR is set to indicate that debug mode has
been requested as a result of the trace count function. The trace counter
allows a minimum of two instructions to be specified for execution prior
to entering trace (specified by a count value of one), unless sequential
breakpoint control operation is enabled in the OCR. In this case, a value
of zero (indicating a single instruction) is allowed.
The PM status field in the OSR indicates that the CPU has entered
debug mode. The following paragraphs discuss conditions that invoke
debug mode.
21.14.9.1 Debug Request During RESET
When the DR bit in the OCR is set, assertion of RESET causes the
device to enter debug mode. In this case the device may fetch the reset
Technical Data MMC2107 – Rev. 2.0
574 JTAG Test Access Port and OnCE MOTOROLA
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