MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
21.14.5 OnCE Decoder (ODEC)
The ODEC receives as input the 8-bit command from the OCMR and
status signals from the processor. The ODEC generates all the strobes
required for reading and writing the selected OnCE registers.
21.14.6 Memory Breakpoint Logic
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Freescale Semiconductor, I
Memory breakpoints can be set for a particular memory location or on
accesses within an address range. The breakpoint logic contains an
input latch for addresses, registers that store the base address and
address mask, comparators, attribute qualifiers, and a breakpoint
counter. Figure 21-11 illustrates the basic functionality of the OnCE
memory breakpoint logic. This logic is duplicated to provide two
independent breakpoint resources.
DSO
DSCK
DSI
ADDR[31:0]
MEMORY ADDRESS LATCH
ADDRESS COMPARATOR
ADDRESS BASE REGISTER X
ADDRESS MASK REGISTER X
BREAKPOINT COUNTER
MATCH
DEC
ATTR
BC[4:0], RCx
MEMORY
BREAKPOINT
QUALIFICATION
BREAKPOINT
MATCH
OCCURRED
COUNT = 0
ISBKPTx
Figure 21-11. OnCE Memory Breakpoint Logic
Technical Data MMC2107 – Rev. 2.0
570 JTAG Test Access Port and OnCE MOTOROLA
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