MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
List of Figures
Figure Title Page
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Freescale Semiconductor, I
16-19 Start Bit Search Example 3 . . . . . . . . . . . . . . . . . . . . . . . .360
16-20 Start Bit Search Example 4 . . . . . . . . . . . . . . . . . . . . . . . .361
16-21 Start Bit Search Example 5 . . . . . . . . . . . . . . . . . . . . . . . .361
16-22 Start Bit Search Example 6 . . . . . . . . . . . . . . . . . . . . . . . .362
16-23 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
16-24 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
16-25 Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . .366
16-26 Loop Operation (LOOPS = 1, RSRC = 0) . . . . . . . . . . . . .367
17-1 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
17-2 SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . .376
17-3 SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . .378
17-4 SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . .379
17-5 SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . .381
17-6 SPI Data Register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . .382
17-7 SPI Pullup and Reduced Drive Register (SPIPURD) . . . . .383
17-8 SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . .384
17-9 SPI Port Data Direction Register (SPIDDR). . . . . . . . . . . .385
17-10 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
17-11 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . .389
17-12 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . .391
17-13 Transmission Error Due to Master/Slave Clock Skew . . . .392
18-1 QADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
18-2 QADC Input and Output Signals . . . . . . . . . . . . . . . . . . . .406
18-3 QADC Module Configuration Register (QADCMCR) . . . . .411
18-4 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .412
18-5 QADC Port QA Data Register (PORTQA) . . . . . . . . . . . . .413
18-6 QADC Port QB Data Register (PORTQB) . . . . . . . . . . . . .413
18-7 QADC Port QA Data Direction Register (DDRQA). . . . . . .415
18-8 QADC Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . .416
18-9 QADC Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . .419
18-10 QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . .422
18-11 QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . . . .427
18-12 Queue Status Transition. . . . . . . . . . . . . . . . . . . . . . . . . . .435
18-13 QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . . . .436
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA List of Figures 33
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