MMC2107 - Freescale Semiconductor

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Timer Modules (TIM1 and TIM2) Freescale Semiconductor, Inc. 15.7.3 Timer Output Compare 3 Mask Register Address: TIM1 — 0x00ce_0002 TIM2 — 0x00cf_0002 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 Write: OC3M3 OC3M2 OC3M1 OC3M0 Reset: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I Read: Anytime Write: Anytime = Writes have no effect and the access terminates without a transfer error exception. Figure 15-4. Timer Output Compare 3 Mask Register (TIMOC3M) OC3M[3:0] — Output Compare 3 Mask Bits Setting an OC3M bit configures the corresponding TIMPORT pin to be an output. OC3Mx makes the timer port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mx bits do not change the state of the TIMDDR bits. 1 = Corresponding TIMPORT pin configured as output 0 = No effect Technical Data MMC2107 – Rev. 2.0 302 Timer Modules (TIM1 and TIM2) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Timer Modules (TIM1 and TIM2) Memory Map and Registers 15.7.4 Timer Output Compare 3 Data Register Address: TIM1 — 0x00ce_0003 TIM2 — 0x00cf_0003 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 Write: OC3D3 OC3D2 OC3D1 OC3D0 Reset: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I Read: Anytime Write: Anytime = Writes have no effect and the access terminates without a transfer error exception. Figure 15-5. Timer Output Compare 3 Data Register (TIMOC3D) OC3D[3:0] — Output Compare 3 Data Bits When a successful channel 3 output compare occurs, these bits transfer to the timer port data register if the corresponding OC3Mx bits are set. NOTE: A successful channel 3 output compare overrides any channel 2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. MMC2107 – Rev. 2.0 Technical Data MOTOROLA Timer Modules (TIM1 and TIM2) 303 For More Information On This Product, Go to: www.freescale.com
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