MMC2107 - Freescale Semiconductor

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Clock Module Freescale Semiconductor, Inc. In stop mode, if the PLL is intentionally disabled, then the LOCKS bit reflects the value prior to entering stop mode. However, if FWKUP is set, then LOCKS is cleared until the PLL regains lock. Once lock is regained, the LOCKS bit reflects the value prior to entering stop mode. Furthermore, reading the LOCKS bit at the same time that the PLL loses lock does not return the current loss of lock condition. In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and 1:1 PLL mode, LOCKS is set after reset. nc... Freescale Semiconductor, I LOCK — PLL Lock Flag 1 = PLL locked 0 = PLL not locked The LOCK flag is set when the PLL is locked. PLL lock occurs when the synthesized frequency is within approximately 0.75 percent of the programmed frequency. The PLL loses lock when a frequency deviation of greater than approximately 1.5 percent occurs. Reading the LOCK flag at the same time that the PLL loses lock or acquires lock does not return the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. LOCS — Sticky Loss Of Clock Flag 1 = Loss of clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with FWKUP = 1 0 = Loss of clock not detected since exiting reset The LOCS flag is a sticky indication of whether a loss of clock condition has occurred at any time since exiting reset in normal PLL and 1:1 PLL modes. LOCS = 0 when the system clocks are operating normally. LOCS = 1 when system clocks have failed due to a reference failure or PLL failure. After entering stop mode with FWKUP set and the PLL and oscillator intentionally disabled (STPMD[1:0] = 11), the PLL exits stop mode in SCM while the oscillator starts up. During this time, LOCS is temporarily set regardless of LOCEN. It is cleared once the oscillator comes up and the PLL is attempting to lock. If a read of the LOCS flag and a loss of clock condition occur simultaneously, the flag does not reflect the current loss of clock condition. Technical Data MMC2107 – Rev. 2.0 232 Clock Module MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Clock Module Memory Map and Registers A loss of clock condition can be detected only if LOCEN = 1 or the oscillator has not yet returned from exit from stop mode with FWKUP = 1. NOTE: The LOCS flag is always 0 in external clock mode. 10.7.2.3 Synthesizer Test Register The synthesizer test register (SYNTR) is only for factory testing. When not in test mode, SYNTR is read-only. nc... Freescale Semiconductor, I Address: 0x00c3_0003 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 = Writes have no effect and the access terminates without a transfer error exception. Figure 10-4. Synthesizer Test Register (SYNTR) MMC2107 – Rev. 2.0 Technical Data MOTOROLA Clock Module 233 For More Information On This Product, Go to: www.freescale.com
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