MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Interrupt Controller Module
Functional Description
7.8.4 Interrupt Configuration
After reset, all interrupts are disabled by default. To properly configure
the system to handle interrupt requests, configuration must be
performed at three levels:
• M•CORE processor
• Interrupt controller
• Local interrupt sources
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7.8.4.1 M•CORE Processor Configuration
Configure the M•CORE first, the interrupt controller second, and the
local interrupt sources last.
For fast interrupts, set the FIE[x] bit in FIER in the M•CORE processor.
For normal interrupts, set the NIE[x] bit. Both FIE and NIE are cleared at
reset. To allow long latency, multicycle instructions to be interrupted
before completion, set the IC bit.
VBR in the M•CORE processor defines the base address of the
exception vector table. If autovectors are to be used, then initialize the
INT and FINT autovectors (vector numbers 10 and 11, respectively). If
vectored interrupts are to be used, then initialize the vectored interrupts
(vector numbers 32–63 and/or 64–95). Whether 32 or 64 vectors are
required depends on whether the fast interrupts share vectors with the
normal interrupt sources based on the FVE bit in the interrupt controller
ICR.
For each vector number, create an interrupt service routine to service
the interrupt, clear the local interrupt flag, and return from the interrupt
routine.
7.8.4.2 Interrupt Controller Configuration
By default, each interrupt source to the interrupt controller is assigned a
priority level of 0 and disabled. Each interrupt source can be
programmed to one of 32 priority levels and enabled as either a fast or
normal interrupt source. Also, the FVE and AE bits in ICR can be
programmed to select autovectored/vectored interrupts and also
determine if the fast interrupt vector number is to be separate from the
normal interrupt vector.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Interrupt Controller Module 171
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