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MT8206<br />
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE<br />
Rs<br />
Top. 1 A B<br />
Top. 2<br />
MT8202<br />
Table 1-5. Signal Topology – SDR<br />
Signal<br />
Trace<br />
Length<br />
(Inch)<br />
Rs<br />
A B<br />
Fig. 1-4 Signal Topologies<br />
C<br />
D<br />
System Memory<br />
(SDR)<br />
DQ CLK DQM RA/Command<br />
Top. 1 Top. 2 Top. 2 Top. 2<br />
Min. Max. Min. Max. Min. Max. Min. Max.<br />
A 0.2 1.3 0.2 1 0.2 1.6 0.2 1<br />
B 0.2 2.4 0.2 1 0.2 1 0.2 1<br />
C 0.2 1.6 0.2 1.6 0.2 1.6<br />
D 0.2 1.6 0.2 1.6 0.2 1.6<br />
Rs ( ) 47 22 22 22<br />
A+B+C (D) 0.4 2.7 1.2 3.2 1 3.2 0.6 3<br />
Note<br />
1. Keep the length of the branches as the same length (C = D), or within 0.2 inches as<br />
possible.<br />
2. Keep the maximum difference of the signal length within 300mil of the same group to meet<br />
the minimum timing skew requirement.<br />
3. It was suggested to keep the spacing between the nearby signals above 2 times of the<br />
trace width as possible.<br />
9.3. LVDS SIGNAL PCB LAYOUT GUIDELINE<br />
For the other applications of the high-speed signal PCB design, below illustrated the<br />
topologies and constraints of the LVDS or other differential signals that were achieved to the<br />
electrical requirements. Also refer to the form to the detail recommendations.<br />
Multi-Layer PCB Design<br />
By the default multi-layers PCB architecture, the inner layers were assigned to be the<br />
June, 2006
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