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MT8206<br />
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE<br />
Rs<br />
MT8202 A B<br />
Table 1-4. Signal Topology –3<br />
Trace Length (inch)<br />
Trace (mil)<br />
A<br />
B<br />
C D<br />
A+B+C(or D)<br />
Fig. 1-4 Signal Topology -3<br />
Signal CLK CLK# CKE<br />
Width 6 6<br />
C<br />
D<br />
DDR<br />
Spacing 20 2*W or Above<br />
Min. 0.2 0.2<br />
Max. 1.2 1.2<br />
Min. 0.2 0.2<br />
Max. 1 1<br />
Min. 0.2 0.2<br />
Max. 1.2 1.2<br />
Min. 0.6 0.6<br />
Max. 2.6 3.2<br />
Rs ( ) 22 22<br />
Note<br />
1. The length difference of the C D shall be within 200mils.<br />
2. The trace length difference of CLK CLK# shall be as short as possible.<br />
3. Keep the trace difference between CLK pair to DQS signals as small as possible.<br />
4. Keep the trace difference between CLK pair to RA / Command signals as small as<br />
possible.<br />
System SDR Memory Solution Space<br />
Refer to the diagrams below to the topologies of the SDR signals, and the actual<br />
dimension specifications were listed of the tables. By the experiments, the target impedance of<br />
the SDR signal was designed to be 55 + - 10 , and which was same as the DDR signals<br />
illustrated above. Refer to the Fig. 1-1 and table. 1-1 for the board stackup.<br />
� SDR Signal Topology<br />
June, 2006
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