You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
MT8206<br />
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE<br />
Table 1-3. Signal Topology –2<br />
Trace (mil)<br />
Trace Length (inch)<br />
B<br />
C<br />
D E<br />
Signal DQM RA / BA CS# CAS# RAS# WE#<br />
A<br />
A+B+D(o<br />
Width 6 6 6<br />
Spacing 2*W or Above 2*W or Above 2*W or Above<br />
Min. 0.2 0.2 0.2<br />
Max. 1 1.2 1.2<br />
Min. 0.2 0.2 0.2<br />
Max. 1 1 1<br />
Min. 0.1 0.1 0.1<br />
Max. 0.5 0.5 0.5<br />
Min. 0.2 0.2 0.2<br />
Max. 1.4 1.2 1.2<br />
Min. 0.6 0.6 0.6<br />
r E) Max. 2.8 3.2 3.2<br />
Rs ( ) 22 22 22<br />
Rt ( ) 75 75 75<br />
Note<br />
1. Keep the difference of the branches’ length D E of the dual loads signal within 100<br />
mils.<br />
2. Put the termination resistor close to the crossing point of the branches.<br />
3. Reversing more spacing to the periodic signal as clock if signal was critical and there<br />
weren’t the guard traces.<br />
4. Put an integrated plane as the return path to the signals beneath the address<br />
command signals.<br />
5. When the signal need to change layers, and the reference paths beneath the signal<br />
are not continued, placing the bypass capacitors nearing to the vias where are the<br />
points to change layers and connecting the capacitors to the different reference<br />
paths.<br />
6. If the DQM Signal used as the dual load topology shown above of Fig. 1-3. Treating<br />
the DQM signal topology as the table 1-3 of signal topology – 2.<br />
� DDR Signal Topology – 3<br />
June, 2006