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MT8206<br />
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE<br />
Trace (mil)<br />
Trace Length (inch)<br />
A<br />
B<br />
C<br />
A+B<br />
MT8202<br />
Signal DQ DQS<br />
Width 6 6<br />
Spacing 2*W or Above 2*W or Above<br />
Min. 0.2 0.2<br />
Max. 2 2<br />
Min. 0.2 0.2<br />
Max. 1.2 1.2<br />
Min. 0.1 0.1<br />
Max. 0.5 0.5<br />
Min. 0.4 0.4<br />
Max. 3 3<br />
Rs ( ) 47 47<br />
Rt ( ) 75 75<br />
Note<br />
1. Keep the difference of the trace length of the same data signal groups within about<br />
200 mils as possible.<br />
2. Keep the difference of the data signal groups within 500 mils as possible (The<br />
longest signal trace to the shortest signal trace).<br />
3. Placing the damping resistor close to the controller IC<br />
4. Placing the termination resistor close to the memory as possible.<br />
5. Put an integrated plane as the return path to the signals beneath the data signals.<br />
6. When the signal needs to change layers and the reference paths beneath the<br />
signal are not continued. Placing the bypass capacitors nearing to the vias where<br />
are the points to change layers and connecting the capacitors to the different<br />
reference paths.<br />
� DDR Signal Topology – 2<br />
Rs<br />
A B<br />
Rt<br />
V TT<br />
C<br />
Fig. 1-3 Signal Topology -2<br />
D<br />
E<br />
DDR<br />
June, 2006
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