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MT8206<br />
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE<br />
Refer to the Fig. 1-1 above. The dielectrics between conductors were as the isolators,<br />
which were used to separate the conductors. By the microstrip line architecture of system<br />
memory signals, the target impedance was desired to have 55 +/- 10%. Please refer to the<br />
table 1 below for your PCB design and recommendation. The default design was 6-mil trace<br />
width with 4.5 mil high dielectrics.<br />
Table 1-1. 4 Layer PCB Stack up Configurations<br />
Trace Width<br />
(mil)<br />
9.2 DDR/SDR DRAM LAYOUT GUIDE<br />
PCB Parameter<br />
H (mil) Target Impedance ( ) Tolerance<br />
5 4 55 10 %<br />
6 4.5 55 10 %<br />
8 7 55 10 %<br />
System DDR Memory Solution Space<br />
Refer to the diagrams below to the topologies of the DDR signals, and the actual<br />
dimension specifications were listed of the tables.<br />
� DDR Signal Topology – 1<br />
Table 1-2. Signal Topology –1<br />
Rs<br />
A B<br />
Rt<br />
V TT<br />
C<br />
Fig. 1-2 Signal Topology -1<br />
DDR<br />
June, 2006
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