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MT8206<br />
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE<br />
Item Symbol Pin # Type Description<br />
6 HDMISD2 AA23<br />
7 HDMISD3 AA24<br />
1 CCIR_VCLK W23<br />
2 CCIR_V0 Y26<br />
3 CCIR_V1 Y25<br />
4 CCIR_V2 Y24<br />
5 CCIR_V3 Y23<br />
6 CCIR_V4 W26<br />
7 CCIR_V5 W25<br />
8 CCIR_V6 W24<br />
9 CCIR_V7 V24<br />
1 DE C6 O<br />
1) GPIO (default, input in initial state)<br />
2) CH 5/6 data input for HDMI<br />
1) GPIO (default, input in initial state)<br />
2) CH 7/8 data input for HDMI<br />
CCIR Interface (9)<br />
2 VSYNCO B6 O Vertical sync, 2mA<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 clock input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data0 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data1 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data2 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data3 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data4 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data5 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data6 input from external TVD<br />
1) GPIO (default, input in initial state)<br />
2) CCIR656 data7 input from external TVD<br />
TTL Interface (4)<br />
1) GPIO (default, input in initial state)<br />
2) Data enable, 2mA<br />
3 HSYNCO A6 O Horizontal sync, 2mA<br />
4 VCLK D6 O<br />
Works in stand-by mode<br />
1) GPIO (default, input in initial state)<br />
2) Video output reference clock, 10mA<br />
ANALOG (117)<br />
PLL Group (12)<br />
1 TP3 C23 I/O Positive PLL group test pin<br />
2 TN3 D22 I/O Negative PLL group test pin<br />
3 PLLVSS1 B23 GND PLL group ground<br />
June, 2006