logic gates 4.5.pdf

AIT Digital Electronics
Simulation Lab
Logic Gates 4.5
CMOS Inverter Power Dissipation
Name
Date
In this lab we will look at the transistor level operation of a basic CMOS inverter and the factors that affect
the power dissipation
of a CMOS inverter.
1. Build the
circuit shown
in MultiSim.
Use Virtual
MOS_4TEP_Virtual (this is a 4 terminal, enhancement mode P channel MOSFET) and a
MOS_TEN_Virtual (this is a 4 terminal, enhancement mode N channel MOSFET). The current
meter is there to monitor I dd (which is the current drawn by the CMOS inverter).
2. Setup the input voltage source (Vin on schematic as a “clock source” with 5V value) as shown. Run
the simulation and view the output voltage on the scope display. Check to make sure there is a clean
square wave pulse at the inverter output (CHB on the oscilloscope)
3. Now adjust V dd and run the simulation noting I dd and calculating P dissipated . Let the simulation run for a
few seconds before reading I dd The value will fluctuate a bit so make an estimate as best as possible.
5.00 V
4.50 V
4.00 V
3.50 V
3.00 V
2.50 V
2.00 V
V dd I dd (uA) P dissipated =I dd X V dd (uW)
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4. Using Excel plot P dissipated vs. V dd .
If you were to write an equation for this curve/line, would P dissipated be a function of V or V 2 ?
5. Now set V dd back to 5.0 V and run the simulation while varying the Vin frequency as the dependent
parameter. Note I dd and calculate P dissipated as before.
Vin Frequency f (Hz) I dd (uA) P dissipated =I dd X V dd (uW)
1000
10000
100000
6. Using Excel plot P dissipated vs. V in frequency (f).
7. If you were to write an equation for this curve/line, would P dissipated be a function of f or f 2 ?
8. Based on your analysis, comment on the effect of clock speed (frequency) and power supply voltage (V dd )
on the power dissipation for a large multi-gate CMOS IC.
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