DAC7631 - dreamm
DAC7631 - dreamm
DAC7631 - dreamm
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+V<br />
+V<br />
+2.5V<br />
OPA2350<br />
2200pF<br />
100Ω<br />
1000pF<br />
1<br />
2<br />
3<br />
4<br />
V REF H <strong>DAC7631</strong><br />
V REF H Sense<br />
V REF L<br />
V REF L Sense<br />
FIGURE 10. Single-supply Buffered V REF H.<br />
LE (LSB)<br />
DLE (LSB)<br />
2.5<br />
2.0<br />
1.5<br />
1.0<br />
0.5<br />
0<br />
–0.5<br />
–1.0<br />
–1.5<br />
LINEARITY ERROR AND<br />
DIFFERENTIAL LINEARITY ERROR vs CODE<br />
(DAC A, +25°C)<br />
2.0<br />
1.5<br />
1.0<br />
0.5<br />
0<br />
–0.5<br />
–1.0<br />
–1.5<br />
–2.0<br />
0000 H 2000 H 4000 H 6000 H 8000 H<br />
Digital Input Code<br />
FIGURE 11. Linearity and Differential Error Curves for<br />
Figure 10.<br />
LE (LSB)<br />
DLE (LSB)<br />
2.5<br />
2.0<br />
1.5<br />
1.0<br />
0.5<br />
0<br />
–0.5<br />
–1.0<br />
–1.5<br />
–2.0<br />
–2.5<br />
LINEARITY ERROR AND<br />
DIFFERENTIAL LINEARITY ERROR vs CODE<br />
(DAC A, +25°C)<br />
2.0<br />
1.5<br />
1.0<br />
0.5<br />
0<br />
–0.5<br />
–1.0<br />
–1.5<br />
–2.0<br />
0000 H 2000 H 4000 H 6000 H 8000 H<br />
Digital Input Code<br />
A000 H C000 H E000 H FFFF H<br />
FIGURE 13. Linearity and Differential Error Curves for<br />
Figure 12.<br />
1<br />
V REF H<br />
V CC<br />
20<br />
+<br />
0.1µF 1µF<br />
2<br />
V REF H Sense<br />
AGND<br />
19<br />
3<br />
V REF L<br />
V SS<br />
18<br />
4<br />
V REF L Sense<br />
V OUT Sense<br />
17<br />
Serial Data Out<br />
5<br />
6<br />
7<br />
DGND<br />
V CC<br />
SDO<br />
A000 H C000 H E000 H FFFF H<br />
Reset DAC Registers<br />
+5V<br />
+V<br />
+2.5V<br />
<strong>DAC7631</strong><br />
V OUT<br />
NC<br />
RSTSEL<br />
16<br />
15<br />
14<br />
V OUT<br />
Serial Data In<br />
Clock<br />
Chip Select<br />
8<br />
9<br />
10<br />
SDI<br />
CLK<br />
CS<br />
RST<br />
LOAD<br />
LDAC<br />
13<br />
12<br />
11<br />
Load<br />
Load DAC Registers<br />
FIGURE 12. Low cost Single-supply Configuration.<br />
Data is shifted into the device through the SDI and CLK pins<br />
and arrives in a shift register. Once all 16 bits have been<br />
transferred, the LOAD pin, which is level-sensitive, should<br />
be brought low to latch the data into a buffer register called<br />
the DAC input register. To latch the new data into the DAC<br />
itself, the LDAC pin, which is edge-sensitive, must be<br />
brought high. When this is done, the DAC will assume the<br />
new value and the output voltage will change (provided that<br />
the new value is different from the old one). Note that<br />
settling time is measured from the time that the LDAC pin<br />
is brought high, since the device’s output does not begin to<br />
change until then.<br />
The <strong>DAC7631</strong>’s double-buffering scheme allows the device<br />
to be updated through the serial interface without disturbing<br />
the voltage on the output pin. It also allows the user to use<br />
separate logic for driving the serial input and triggering<br />
15<br />
<strong>DAC7631</strong><br />
®