DAC7631 - dreamm

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+V OPA2350 2kΩ 2200pF 100Ω +2.5V +0.050V +V 98kΩ 100Ω 1000pF 1 2 3 4 V REF H DAC7631 V REF H Sense V REF L V REF L Sense 2200pF 1000pF NOTE: V REF L has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. FIGURE 6. Single-supply Buffered Reference, V REF L = 50mV. LE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000 H 2000 H 4000 H 6000 H 8000 H Digital Input Code LE (LSB) DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 A000 H C000 H E000 H FFFF H 0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000 H E000 H FFFF H Digital Input Code FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 6. FIGURE 8. Integral Linearity and Differential Linearity Error Curves for Figure 9. +V +V OPA2350 +1.25V 2200pF 100Ω +V 100Ω 1000pF 1 2 3 4 V REF H DAC7631 V REF H Sense V REF L V REF L Sense +2.5V 2200pF 1000pF FIGURE 9. Single-supply Buffered Reference, V REF L = +1.25V, V REF H = –1.25V. ® DAC7631 14
+V +V +2.5V OPA2350 2200pF 100Ω 1000pF 1 2 3 4 V REF H DAC7631 V REF H Sense V REF L V REF L Sense FIGURE 10. Single-supply Buffered V REF H. LE (LSB) DLE (LSB) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000 H 2000 H 4000 H 6000 H 8000 H Digital Input Code FIGURE 11. Linearity and Differential Error Curves for Figure 10. LE (LSB) DLE (LSB) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000 H 2000 H 4000 H 6000 H 8000 H Digital Input Code A000 H C000 H E000 H FFFF H FIGURE 13. Linearity and Differential Error Curves for Figure 12. 1 V REF H V CC 20 + 0.1µF 1µF 2 V REF H Sense AGND 19 3 V REF L V SS 18 4 V REF L Sense V OUT Sense 17 Serial Data Out 5 6 7 DGND V CC SDO A000 H C000 H E000 H FFFF H Reset DAC Registers +5V +V +2.5V DAC7631 V OUT NC RSTSEL 16 15 14 V OUT Serial Data In Clock Chip Select 8 9 10 SDI CLK CS RST LOAD LDAC 13 12 11 Load Load DAC Registers FIGURE 12. Low cost Single-supply Configuration. Data is shifted into the device through the SDI and CLK pins and arrives in a shift register. Once all 16 bits have been transferred, the LOAD pin, which is level-sensitive, should be brought low to latch the data into a buffer register called the DAC input register. To latch the new data into the DAC itself, the LDAC pin, which is edge-sensitive, must be brought high. When this is done, the DAC will assume the new value and the output voltage will change (provided that the new value is different from the old one). Note that settling time is measured from the time that the LDAC pin is brought high, since the device’s output does not begin to change until then. The DAC7631’s double-buffering scheme allows the device to be updated through the serial interface without disturbing the voltage on the output pin. It also allows the user to use separate logic for driving the serial input and triggering 15 DAC7631 ®
Page 1 and 2: ® DAC7631 ® DAC7631 For most curr
Page 3 and 4: SPECIFICATIONS (Single Supply) At T
Page 5 and 6: PIN CONFIGURATION PIN DESCRIPTIONS
Page 7 and 8: TYPICAL PERFORMANCE CURVES: V SS =
Page 13: The current into the V REF H input
Page 17 and 18: SDI (MSB) D15 (LSB) D14 D13 D12 D11
Page 19 and 20: PACKAGE OPTION ADDENDUM www.ti.com

DAC7631 - dreamm

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