DAC7631 - dreamm

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+5V +2.5000V 1 2 V REF H V REF H Sense V CC AGND 20 19 + 0.1µF 1µF 3 V REF L V SS 18 Serial Data Out 4 5 6 7 V REF L Sense V OUT Sense DGND DAC7631 V OUT V DD NC SDO RSTSEL 17 16 15 14 0V to +2.5V Serial Data In Clock Chip Select 8 9 10 SDI CLK CS RST LOAD LDAC 13 12 11 Reset DAC Registers Load Load DAC Registers FIGURE 2. Basic Single-Supply Operation. +5V +5V + 0.1µF 1µF +2.5000V –2.5000V Serial Data Out 1 2 3 4 5 6 7 V REF H V REF H Sense V REF L V REF L Sense V CC AGND V SS V OUT Sense DGND DAC7631 V OUT V DD NC SDO RSTSEL 20 19 18 17 16 15 14 + 0.1µF 1µF + 0.1µF 1µF –5V –2.5V to +2.5V Serial Data In Clock Chip Select 8 9 10 SDI CLK CS RST LOAD LDAC 13 12 11 Reset DAC Registers Load Load DAC Registers FIGURE 3. Basic Dual-Supply Operation. ANALOG OUTPUTS When V SS = –5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, guaranteed over the –40°C to +85°C temperature range. When V SS = 0V (single-supply operation), and with R LOAD also connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error when V SS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000 H , 0001 H , 0002 H , etc.) if the output amplifier has a negative offset. At the negative limit of –2mV, the first specified output starts at code 0040 H . Due to the high accuracy of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 2.5V fullscale range has a 1LSB value of 38µV. With a load current of 1mA, series wiring and connector resistance of only 40mΩ (R W2 ) will cause a voltage drop of 40µV, as shown in Figure 4. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copperclad printed circuit board is 1/2 mΩ per square. For a 1mA load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30µV. The DAC7631 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 4), thus ensuring an accurate output voltage. REFERENCE INPUTS The reference inputs, V REF L and V REF H, can be any voltage between V SS + 2.5V and V CC – 2.5V, provided that V REF H is at least 1.25V greater than V REF L. The minimum output of each DAC is equal to V REF L plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to V REF H plus a similar offset voltage. Note that V SS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on V SS sets several bias points within the converter. If V SS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. ® DAC7631 12
The current into the V REF H input and out of V REF L depends on the DAC output voltage, and can vary from a few microamps to approximately 0.3mA in dual supply or 0.15mA in single-supply operation. The reference input appears as a varying load to the reference. If the reference can sink or source the required current, a reference buffer is not required. The DAC7631 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 13 show different reference configurations, and the effect on the linearity and differential linearity. DIGITAL INTERFACE Table I shows the basic control logic for the DAC7631. The interface consists of a serial clock input (CLK), serial data input (SDI), DAC input register load control signal (LOAD), and DAC load control signal (LDAC). In addition, a chip select input (CS) is provided to simplify device selection in systems with multiple devices. An asynchronous reset input (RST), triggered by a rising edge, is provided to force startup conditions, periodic resets, or emergency resets to a known state. The action of RST can be selected using the reset select (RSTSEL) pin. SERIAL DATA INPUT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 INPUT DAC CS RST RSTSEL LDAC LOAD REGISTER REGISTER MODE L H X X L Write Hold Write Input H H X ↑ H Hold Write Update H H X H H Hold Hold Hold X ↑ L X X Reset to Zero Reset to Zero Reset to Zero X ↑ H X X Reset to Midscale Reset to Midscale Reset to Midscale TABLE I. DAC7631 Logic Truth Table. +5V +V 1 V REF H V CC 20 + 0.1µF 1µF +2.5V 2 3 V REF H Sense V REF L AGND V SS 19 18 R W1 Serial Data Out 4 5 6 7 V REF L Sense V OUT Sense DGND DAC7631 V DD SDO V OUT NC RSTSEL 17 16 15 14 R W2 V OUT Serial Data In Clock Chip Select 8 9 10 SDI CLK CS RST LOAD LDAC 13 12 11 Reset DAC Registers Load Load DAC Registers FIGURE 4. Analog Output Closed-loop Configuration. R W1 and R W2 represent wiring resistance. +V +V OPA2234 +2.5V 2200pF 100Ω 1000pF 1 2 DAC7631 V REF H V REF H Sense 3 V REF L 4 V REF L Sense 100Ω –2.5V 2200pF 1000pF –V –V FIGURE 5. Dual-supply Buffered References. 13 DAC7631 ®
Page 1 and 2: ® DAC7631 ® DAC7631 For most curr
Page 3 and 4: SPECIFICATIONS (Single Supply) At T
Page 5 and 6: PIN CONFIGURATION PIN DESCRIPTIONS
Page 7 and 8: TYPICAL PERFORMANCE CURVES: V SS =
Page 9 and 10: TYPICAL PERFORMANCE CURVES: V SS =
Page 11: TYPICAL PERFORMANCE CURVES: V SS =
Page 15 and 16: +V +V +2.5V OPA2350 2200pF 100Ω 10
Page 17 and 18: SDI (MSB) D15 (LSB) D14 D13 D12 D11
Page 19 and 20: PACKAGE OPTION ADDENDUM www.ti.com

DAC7631 - dreamm

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