16-Bit, Ultra-Low Power, Voltage Output Digital-to-Analog ... - dreamm

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DAC8830 DAC8831 SLAS449B–FEBRUARY 2005–REVISED APRIL 2006 www.ti.com CS DAC Updated t Delay t Lead t wsck t td t sck t wsck t Lag t DSCLK SCLK t su tho SDI BIT15 (MSB) BIT14 BIT13, . . . ,1 BIT0 −−−Don’t Care Figure 1. DAC8830 Timing Diagram Case 1: LDAC tied to LOW CS DAC Updated t Delay t Lead t wsck t td t sck t wsck t Lag t DSCLK SCLK t su tho SDI BIT 15 (MSB) BIT 14 BIT 13, . . . ,1 BIT 0 LDAC LOW −−−Don’t Care Lead t wsck Case 2: LDAC Active t td t Delay t t sck CS t wsck t Lag t DSCLK SCLK t su tho SDI BIT 15 (MSB) BIT 14 BIT 13, . . . ,1 BIT 0 LDAC LOW t DLADC t WLDAC −−−Don’t Care DAC Updated Figure 2. DAC8831 Timing Diagram 6 Submit Documentation Feedback
DAC8830 DAC8831 www.ti.com SLAS449B–FEBRUARY 2005–REVISED APRIL 2006 TIMING CHARACTERISTICS: V DD = +5 V (1)(2) At –40°C to +85°C, unless otherwise noted. TIMING CHARACTERISTICS: V DD = +3 V (1)(2) At –40°C to +85°C, unless otherwise noted. PARAMETER MIN MAX UNIT t sck SCLK period 20 ns t wsck SCLK high or low time 10 ns t Delay Delay from SCLK high to CS low 10 ns t Lead CS enable lead time 10 ns t Lag CS enable lag time 10 ns t DSCLK Delay from CS high to SCLK high 10 ns t td CS high between active period 30 ns t su Data setup time (input) 10 ns t ho Data hold time (input) 0 ns t WLDAC LDAC width 30 ns t DLDAC Delay from CS high to LDAC low 30 ns V DD high to CS low (power-up delay) 10 µs (1) Assured by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter. PARAMETER MIN MAX UNIT t sck SCLK period 20 ns t wsck SCLK high or low time 10 ns t Delay Delay from SCLK high to CS low 10 ns t Lead CS enable lead time 10 ns t Lag CS enable lag time 10 ns t DSCLK Delay from CS high to SCLK high 10 ns t td CS high between active period 30 ns t su Data setup time (input) 10 ns t ho Data hold time (input) 0 ns t WLDAC LDAC width 30 ns t DLDAC Delay from CS high to LDAC low 30 ns V DD high to CS low (power-up delay) 10 µs (1) Assured by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter. Submit Documentation Feedback 7
Page 1 and 2: ® OPA132 IVC102 DAC8831 DAC88
Page 3 and 4: www.ti.com DAC8830 DAC8831 SLAS449B
Page 5: DAC8830 DAC8831 www.ti.com PIN CONF
Page 9 and 10: www.ti.com At T A = +25°C, V REF =
Page 15 and 16: www.ti.com THEORY OF OPERATION DAC8
Page 17 and 18: DAC8830 DAC8831 www.ti.com SLAS449B
Page 19 and 20: www.ti.com Bipolar Output Operation
Page 21 and 22: www.ti.com CROSS-REFERENCE The DAC8
Page 25: IMPORTANT NOTICE Texas Instruments

16-Bit, Ultra-Low Power, Voltage Output Digital-to-Analog ... - dreamm

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