16-Bit, Ultra-Low Power, Voltage Output Digital-to-Analog ... - dreamm

DAC8830
DAC8831
www.ti.com
PIN CONFIGURATION (NOT TO SCALE)
SLAS449B–FEBRUARY 2005–REVISED APRIL 2006
D PACKAGE D PACKAGE RGY PACKAGE
SO-8 SO-14 QFN-14
(TOP VIEW) (TOP VIEW) (TOP VIEW)
V OUT
AGND
V REF
CS
1
2
3
4
DAC8830
8
7
6
5
V DD
DGND
SDI
SCLK
RFB
V OUT
AGNDF
AGNDS
V REF −S
V REF −F
CS
1
2
3
4
5
6
7
DAC8831
14
13
12
11
10
9
8
V DD
INV
DGND
LDAC
SDI
NC
SCLK
V DD
14
INV
DGND
LDAC
SDI
DAC8831
Thermal Pad (1)
NC
13 12 11 10 9
8
SCLK
RFB
1
7
CS
2 3 4 5 6
V OUT
AGNDF
AGNDS
V REF −S
V REF −F
NOTE: (1) Exposed thermal pad in the QFN package
must be connected to analog ground.
TERMINAL FUNCTIONS
TERMINAL
NO. NAME
DESCRIPTION
DAC8830
1 V OUT Analog output of DAC
2 AGND Analog ground
3 V REF Voltage reference input
4 CS Chip select input (active low). Data is not clocked into SDI unless CS is low
5 SCLK Serial clock input
6 SDI Serial data input. Data is latched into input register on the rising edge of SCLK.
7 DGND Digital ground
8 V DD Analog power supply, +3 V to +5 V
DAC8831
1 RFB Feedback resistor. Connect to the output of external operational amplifier in bipolar mode.
2 V OUT Analog output of DAC
3 AGNDF Analog ground (Force)
4 AGNDS Analog ground (Sense)
5 V REF- S Voltage reference input (Sense). Connect to external voltage reference
6 V REF- F Voltage reference input (Force). Connect to external voltage reference
7 CS Chip select input (active low). Data is not clocked into SDI unless CS is low.
8 SCLK Serial clock input.
9 NC No internal connection
10 SDI Serial data input. Data is latched into input register on the rising edge of SCLK.
11 LDAC
Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the
content of the input register.
12 DGND Digital ground
13 INV
Junction point of internal scaling resistors. Connect to external operational amplifier inverting input in bipolar
mode.
14 V DD Analog power supply, +3 V to +5 V.
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