16-Bit, Ultra-Low Power, Voltage Output Digital-to-Analog ... - dreamm

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DAC8830 DAC8831 SLAS449B–FEBRUARY 2005–REVISED APRIL 2006 At T A = +25°C, V REF = +2.5 V unless otherwise noted TYPICAL CHARACTERISTICS: V DD = +3 V (continued) www.ti.com 300 REFERENCE CURRENT vs CODE (BIPOLAR MODE) V REF = 1.5 V DIGITAL FEEDTHROUGH V REF = 2.5 V Reference Current (µA) 250 200 150 100 50 5V/div 20mV/div SDI V OUT 0 0 8192 16384 24576 32768 40960 Digital Input Code 49152 57344 65536 Time (50ns/div) Figure 38. Figure 39. MAJOR-CARRY GLITCH (FALLING) MAJOR-CARRY GLITCH (RISING) V REF = 2.5 V V REF = 2.5 V 5V/div LDAC 5V/div LDAC 0.1V/div V OUT 0.1V/div V OUT Time (0.5µs/div) Time (0.5µs/div) Figure 40. Figure 41. DAC SETTLING TIME (FALLING) DAC SETTLING TIME (RISING) V REF = 2.5 V V REF = 2.5 V 5V/div LDAC 5V/div LDAC 1V/div V OUT V OUT 1V/div Time (0.2µs/div) Time (0.2µs/div) Figure 42. Figure 43. 14 Submit Documentation Feedback
www.ti.com THEORY OF OPERATION DAC8830 DAC8831 SLAS449B–FEBRUARY 2005–REVISED APRIL 2006 GENERAL DESCRIPTION The DAC8830 and DAC8831 are single, 16-bit, serial-input, voltage-output DACs. They operate from a single supply ranging from 2.7 V to 5 V, and typically consume 5 µA. Data is written to these devices in a 16-bit word format, via an SPI serial interface. To ensure a known power-up state, these parts are designed with a power-on reset function. The DAC8830 and DAC8831 are reset to zero code. In unipolar mode, the DAC8830 and DAC8831 are reset to 0V, and in bipolar mode, the DAC8831 is reset to –V REF . Kelvin sense connections for the reference and analog ground are included on the DAC8831. DIGITAL-TO-ANALOG SECTIONS The DAC architecture for both devices consists of two matched DAC sections and is segmented. A simplified circuit diagram is shown in Figure 44. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or V REF . The remaining 12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network. R R V OUT 2R 2R 2R 2R 2R 2R 2R S0 S1 S11 E1 E2 E15 V REF 12−Bit R−2R Ladder Four MSBs Decoded into 15 Equal Segments Figure 44. DAC Architecture OUTPUT RANGE The output of the DAC is V OUT = (V REF × Code)/65536. Where Code is the decimal data word loaded to the DAC latch. Submit Documentation Feedback 15
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16-Bit, Ultra-Low Power, Voltage Output Digital-to-Analog ... - dreamm

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