Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

Specification
Index 1.01
Project No.
RF-Products, Controller RTRM08 Transceiver Module Easw I 2 C Page 9
Development
Production S. Schreiber 2007-08-24
addressing a slave write transfer
7-bit 0 0 8-bit 0 8-bit 0/1
free S address RW A+ data byte A+ data byte A
addressing a slave read transfer
7-bit 1 0 8-bit 0 8-bit 1
Sr address RW A+ data byte A+ data byte A- P free
from master to slave
from slave to master
Figure 5 Combined write and read transfer using a 7-bit address
S start condition
Sr repeated start condition
RW R/W direction bit
A+ acknowledge-bit (SDA line is low)
A- acknowledge-bit (SDA line is high)
A acknowledge-bit (SDA line is low or high)
P stop condition
Often a master wants to perform a read transfer immediately after a write transfer (Figure 5). The master can
use a repeated start condition Sr in place of a separated stop condition P and a start condition S after the
write transfer and before the read transfer.
Some 7-bit addresses are reserved and are not allowed to be used as slave-address. The 7-bit addresses
11110xx (binary) are not allowed to be used as 7-bit slave address, because they initiate 10-bit addressing,
see below. (Please refer to Philips' I 2 C specification for further information about reserved addresses.)
10-bit addressing
If a master wants to transfer any data to (write) or from (read) a slave that has a 10-bit address, the master
generates a start condition S (or a repeated start condition Sr) to acquire the free bus first (Figure 6). At next
the master transmits the bit pattern 11110 and the two most significant bits of the 10-bit address (most
significant bit at first), which are followed by one R/W-bit. The R/W-bit must be always 0 (means write
transfer) for compatibility with 7-bit addressing, even though there is a read transfer desired. The mentioned
bit pattern, 2 bits of the address, and the R/W-bit are 8 data bits (one byte), which the master transmits.
Each slave has to recognize the start condition S and has to receive the subsequent byte. A slave will check
the bit pattern 11110, compare the received 2-bit part of the address with its own unique address, and check
the R/W-bit. If the two address bits match and R/W is 0, a slave continues receiving the addressing of the
master. Other slaves, which are not addressed, will continue waiting for another start condition S (or a
repeated start condition Sr) including all slaves which have a 7-bit address. Since the 7-bit address 11110xx
is reserved, not any 7-bit slave has a matching address.
With the nineth bit transfer an acknowledge bit A is transferred from a slave to the master (in the opposite
direction to the transfer of the preceding byte). Any addressed slave has to transfer a low acknowledge-bit A+
(means acknowledge). If the master receives a low acknowledge-bit A+, communication will proceed; when
the acknowledge-bit is high (A-), the master has to generate a stop condition P, and the I 2 C-bus enters its
free state.
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