Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT
Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT
Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT
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<strong>Specification</strong><br />
Index 1.01<br />
Project No.<br />
RF-Products, Controller <strong>RTRM08</strong> <strong>Transceiver</strong> <strong>Module</strong> Easw I 2 C Page 8<br />
Development<br />
Production S. Schreiber 2007-08-24<br />
addressing a slave read transfer<br />
7-bit 1 0 8-bit 0 8-bit 1<br />
free S address RW A+ data byte A+ data byte A- P free<br />
from master to slave<br />
from slave to master<br />
Figure 4 Read transfer using a 7-bit address<br />
S start condition<br />
RW R/W direction bit<br />
A+ acknowledge-bit (SDA line is low)<br />
A- acknowledge-bit (SDA line is high)<br />
P stop condition<br />
If it is a write transfer, the master continues transmitting the data bytes which the master wants to write into<br />
the addressed slave (Figure 3). If it is a read transfer, the addressed slave will transmit the data bytes<br />
synchronous to the master according to the serial clock which the master generates (Figure 4). If addressing<br />
<strong>of</strong> a slave went successfully, at least one data byte has to be transferred. The master isn't allowed to<br />
generate a stop condition immediately after transferring the desired slave address.<br />
Data bytes (8 bits) are transferred with their most significant bit at first. After each data byte an acknowledgebit<br />
A is transferred from that device, which received the preceding data byte to the device, which transmitted<br />
the data byte before: the acknowledge-bit is transferred in the opposite direction to the preceding transfer <strong>of</strong><br />
the data byte.<br />
If the master receives a low acknowledge-bit A+ (means acknowledge) while a write transfer, the master can<br />
continue writing into the slave. If the master receives a high acknowledge-bit A- while a write transfer, it will<br />
terminate the transfer with a stop condition P.<br />
If the master transmits a low acknowledge-bit A+ to the slave (means acknowledge) while a read transfer, the<br />
master has to continue reading the slave's data. If the master transmits a high acknowledge-bit A- to the<br />
slave due to any reason while a read transfer, the master has to terminate the transfer with a stop condition P<br />
subsequently.<br />
Each transfer is terminated by the master, which generates a stop condition P. The master also can<br />
terminate a transfer with a repeated start condition Sr which addresses a slave again and initiates a new<br />
transfer. Subsequent to a repeated start condition Sr the sequence is just as after a start condition S.<br />
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