Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT
Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT
Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT
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<strong>Specification</strong><br />
Index 1.01<br />
Project No.<br />
RF-Products, Controller <strong>RTRM08</strong> <strong>Transceiver</strong> <strong>Module</strong> Easw I 2 C Page 6<br />
Development<br />
Production S. Schreiber 2007-08-24<br />
Furthermore, one or more slave devices are connected to the I 2 C-bus, where each slave device must have a<br />
unique I 2 C-address.<br />
An I 2 C bus can be free and there are start conditions, repeated start conditions, stop conditions, and bit<br />
transfers on an I 2 C-bus (Figure 2).<br />
Both SCL and SDA are high while the I 2 C bus is free; all <strong>of</strong> the SCL and SDA outputs are high. (All open-drain<br />
outputs on a line form a wired-AND.)<br />
The start condition S is a falling edge <strong>of</strong> the SDA line, when the SCL line is (still) high. The SCL line is pulled to<br />
low subsequently. A start condition S is generated only by a master.<br />
The SCL line is low before a bit transfer (subsequent to a start condition or a bit transfer). The transmitting<br />
device pulls the SDA line low or releases it to high according to the desired data bit first. At next the master<br />
generates a rising edge on the SCL line and a falling edge on SCL subsequently. (When SCL is high between<br />
the rising and falling edge, SDA must not change its state, because it would generate a start condition or a<br />
stop condition.) The SCL line is low again after transmitting the bit. The SCL line is always driven by the<br />
master, but the SDA line is driven by the transmitting device (either the master or the slave which was<br />
addressed before by the master).<br />
A slave can slow down the transfer by pulling the SCL line to low after the falling edge (clock stretching). The<br />
master has to realize that the slave pulls the SCL line to low. Since the SCL outputs <strong>of</strong> the master and the<br />
slave form a wired-AND, the SCL line will be low until both the master and the slave are able to continue.<br />
The SCL line is low before a stop condition P (subsequent to a bit transfer). The SDA line is pulled to low if it<br />
was not low before. The SCL line is released to high. A rising edge is generated on the SDA line<br />
subsequently; and the I 2 C-bus is free. A stop condition P is generated only by a master.<br />
A master also can generate a repeated start condition Sr that starts a new transfer after the bus has been<br />
acquired. The SDA line is released to high if it was not high before. The SCL line is released to high. A falling<br />
edge is generated on the SDA line subsequently. A stop condition P and a start condtion S, which are<br />
generated by a master, can be replaced by a repeated start condition Sr. A master uses a repeated start<br />
condition Sr in order to start a new transfer, but prevents another master device from acquiring the I 2 C bus.<br />
SDA<br />
SCL<br />
free<br />
bus<br />
start<br />
condition<br />
S<br />
data bit<br />
bit<br />
transfer<br />
Figure 2 I 2 C-bus lines and common conditions<br />
data bit<br />
bit<br />
transfer<br />
another bit<br />
transfers<br />
another bit<br />
transfers<br />
stop<br />
condition<br />
P<br />
repeated start<br />
condition<br />
Sr<br />
free<br />
bus<br />
another bit<br />
transfers<br />
7007