Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

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Specification Index 1.01 Project No. RF-Products, Controller RTRM08 Transceiver Module Easw I 2 C Page 10 Development Production S. Schreiber 2007-08-24 At next the master generates a repeated start condition Sr and transmits the eight remaining least significant bits of the 10-bit address (most significant bit at first). Any slave which was addressed by the two most significant address bits will compare the received eight least significant address bits with its own unique address. If the address bits match, a slave is addressed by the master. Other slaves, which are not addressed, will continue waiting for another start condition S (or a repeated start condition Sr). With the nineth bit transfer an acknowledge bit A is transferred from a slave to the master again (in the opposite direction to the transfer of the preceding byte). The addressed slave has to transfer a low acknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communication will proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and the I 2 C-bus enters its free state. If a write transfer is desired, the master continues transmitting the data bytes and will terminate the transfer exactly as it is described on 7-bit addressing (Figure 6). addressing a slave (high part of address) 2-bit 0 0 8-bit 0 free S 11110 address RW A+ Sr address A+ write transfer 8-bit 0 8-bit 0/1 data byte A+ data byte A from master to slave from slave to master Figure 6 Write transfer using a 10-bit address addressing a slave (low part of address) P free S start condition Sr repeated start condition RW R/W direction bit A+ acknowledge-bit (SDA line is low) A acknowledge-bit (SDA line is low or high) P stop condition If a read transfer is desired, the master generates a repeated start condition Sr after it has addressed a slave (10-bit address) successfully (Figure 7). At next the master transmits the bit pattern 11110, the two most significant bits of the 10-bit address (most significant bit at first), which are followed by one R/W-bit again. The R/W-bit must be 1 now (means read transfer). The slave which was addressed before the repeated start condition Sr (but not any other slave) will check the bit pattern 11110, compare the received 2-bit part of the address with its own unique address, and check the R/W-bit (must be 1) again. If each bit matches, the considered slave is addressed by the master for a read transfer. Other slaves, which are not addressed, will continue waiting for another start condition S (or a repeated start condition Sr). With the nineth bit transfer an acknowledge bit A is transferred again from a slave to the master (in the 7007
Specification Index 1.01 Project No. RF-Products, Controller RTRM08 Transceiver Module Easw I 2 C Page 11 Development Production S. Schreiber 2007-08-24 opposite direction to the transfer of the preceding byte). The addressed slave has to transfer a low acknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communication will proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and the I 2 C-bus enters its free state. The master receives the data bytes from the slave at next and will terminate the transfer exactly as it is described on 7-bit addressing. addressing a slave (high part of address) addressing a slave (low part of address) 2-bit 0 0 8-bit 0 free S 11110 address RW A+ Sr address A+ addressing the slave for read transfer (high part of address) 2-bit 1 0 8-bit 0 8-bit 1 Sr 11110 address RW A+ data byte A+ data byte A- P free from master to slave from slave to master Figure 7 Read transfer using a 10-bit address read transfer S start condition Sr repeated start condition RW R/W direction bit A+ acknowledge-bit (SDA line is low) A- acknowledge-bit (SDA line is high) P stop condition Often a master wants to perform a read transfer immediately after a write transfer (Figure 8). The master can also address a slave (10-bit addressing) for a read transfer immediately after a write transfer was performed. 7007
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Specification of RTRM08 Transceiver Module Easywave I2C - ELDAT

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