Department of Electronics - IPN - IN2P3

General & technical departments
Deparrttmentt off Electtrroni
ics
Contact : P. Edelbruck tél. +33 1 69 15 74 74 (ebk@ipno.in2p3.fr)
Le Service d’Electronique Physique
Le Service d’Electronique Physique a pour mission le développement et la construction d’équipements de mesure et
d’acquisition de données. De nombreux instruments ne sont pas disponibles sur le marché et doivent être conçus et
réalisés à la demande, en vue d’équiper les détecteurs très particuliers de la physique nucléaire. L’activité du
service couvre toutes les phases du développement, depuis l’expression du besoin jusqu’à la fourniture « clé en
main » d’un appareil ou d’un sous-ensemble. Le service comprend 25 personnes dont une douzaine d’ingénieurs
intégrés à des équipes projets. Un groupe est chargé de la conception électromécanique et du développement des
circuits imprimés. Un atelier doté d’une structure d’achat est chargé de la construction des prototypes et de la
sous-traitance des productions en volume. Ces deux dernières années ont vu l’aboutissement de projets importants
dont un détecteur de particules chargées (MUST II) doté d’un ASIC développé avec le CEA. Le détecteur de muons
du projet Alice (10 6 voies) est maintenant en production et le détecteur germanium de grand volume AGATA est en
plein développement avec la perspective de construction de plusieurs milliers de cartes au nouveau standard ATCA.
Mission of the Group
The Electronics Group is composed of 25 persons,
including 12 electronics engineers. Its mission is the design
and the development of electronic equipments associated to
nuclear physics detectors. The activities are centred on
front-end electronics i.e. preamplifiers and signal
conditioning. The tasks range from spectroscopy,
calorimetry and tracking, using charge or energy
measurements for all kind of detectors (gas,
semiconductors, scintillators, PMDs…) to accurate timing
determination using analog and digital circuitry. The group
designs and manufactures complex digital interfaces
between the physics world and the acquisition systems.
From a manufacturing point of view, the group is in charge
of the delivery of the complete system. This is achieved
either using the internal workshop or subcontracting the
manufacturing task to industrial companies. The workshop
provides the necessary means for prototyping and repair
tasks in all cases. Due to the increase of the channel count
and complexity of most modern detectors, instrumentation
often requires the use of custom designed integrated
circuits. A special team with the appropriate design tools
exists for this purpose. Several components have been
successfully designed and manufactured, in collaboration
with other institutes (MUST with CEA) or internally (TDC
for G0, Analog pipe-line for AZ4π).
Teams & Organization
The department has two permanent entities working for all
projects : Design and Workshop. The rest of the staff is
organized in project teams, usually lead by a physicist in
the scope of a physics research project. This organization
changes over time, according to needs. With four persons,
the Design Group is in charge of the “electromechanical”
design of the instruments. Most of the work consists of
printed circuit board design. Three persons with
workstations and Cadence CAD tools are allocated fulltime
to this task. They also take care of the internal
component data base, with a permanent worry of making
manufacturing easy, safe and cost effective. Last but not
least the team is responsible of blueprints production for
manufacturing, of primary importance when the work is
subcontracted. A team of five persons is in charge of
hardware manufacturing and maintenance. Most of the
prototypes of the electronic boards are assembled
internally. Two persons are especially skilled in Surface
Mount Device assembling and repair. A new machine for
repairing Ball Grid Array packages (BGA) has been bought
in 2005. The team also takes care of the management of
external fabrication when quantities are large or a special
technology is required. In the later case, they select the
manufacturer, place the order and provide a total follow up.
ASIC Design
Although belonging to project teams, two engineers are
especially trained in silicon integrated circuits design. The
most recent development is an analog pipeline circuit
aimed to high speed signal sampling. The group has also
provided the design of the analog section of the recent
MUST II chip built in collaboration with CEA (see article
in this issue). The team also contributes to the IN2P3
“0.35μ building block club”. The objective of this
organization is to allow the whole community to reuse fully
documented designs issuing from larger systems designed
in the laboratories. Two original basic bricks have been
submitted so far (Delay Locked Loop and High Speed
Amplifier).
Projects
The electronics for the large muon detector of ALICE (10 6
channels) has now entered its production phase. MUST II is
also completed and the production of 6 units has started.
The AZ4π project represents the R&D phase of the design
of a future charged particle detector (FAZIA) comprising
8000 channels and covering a 4π solid angle. The challenge
here is to perform Charge/Mass identification at high
energy, with high Z nuclei. A special high speed ASIC has
been designed for this purpose. The large volume
germanium detector AGATA will be tested in 2006 with an
electronic system developed with CSNSM and using the
new high speed communication standard ATCA.
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General & technical Departments
The electtrroni
ics off ALIICE dimuon ttrracki ing chamberrs
IPNO Participation : V. Chambert, P. Courtat, S. Drouet, B.-Y. Ky, J-M. Martin, C. Oziol
Collaboration : Institut de Physique Nucléaire d’Orsay, Saha Institute of Nuclear Physics, Istituto
Nazionale di Fisica Nucleare Sezione di Cagliari, Subatech Nantes
L’électronique des chambres à fils du bras Dimuon d’Alice
Le bras Dimuon de l’expérience Alice du Cern comprend entre autres un système de reconstruction de traces des
particules composé de 10 chambres à fils reparties dans 5 stations. L’IPNO a en charge la coordination de
l’électronique pour tout le bras Dimuon, ainsi que la construction de la station 1. Le système de lecture des
chambres comprend des cartes frontales de lecture et de numérisation des données, des bus de transmission vers
les châssis CROCUS de lecture et un châssis de transmission et de mise en forme du trigger. Après une brève
présentation de ces systèmes nous décrirons de façon plus détaillée le système CROCUS.
Electronics architecture
The ALICE dimuon arm is, for the main parts, composed of
several absorbers, of a trigger system, of a dipole and of a
tracking system. The tracking system is composed of five
stations with two chambers for each of them.
IPN Orsay is in charge of the electronics coordination for
the tracking system (fig 1). It means that front-end
electronics (≈20 000 Manu boards, more than 10 6 channels),
CROCUS read out crates (≈ 22 crates), trigger dispatching
crates (2 crates) and the related software were designed at
Orsay and we will produced for the whole Dimuon
collaboration.
Besides these elements, data bus transmission (bus patch)
were designed at Orsay but each station adapted the system
for its needs and produced them.
Orsay is also responsible for the design and production of
transmission boards called translators and bridges both for
station 1 and 2.
CROCUS crate
A rough estimation of the typical information
number to read in the case of a “mean” collision gives
about 150 kB distributed in the five stations. Using a safety
factor of 2, the electronics will have to handle an
acquisition rate of 1200 evts/s for the lead beams and of
DETECTOR
FEE
FEE
2 x 32
PADs
PATCH BUS
Up to 26 or 3 x 17
MANU BOARD.
Up to 100 PATCH BUS
per detector.
HIGH VOLTAGE
MANU
SLOW CONTROL
DETECTOR: Chapter 1
FEE: Chapter 2
MANU: Chapter 2.1
READ OUT: Chapter 3
DISPATCHING: Chapter 3.2
CROCUS: Chapter 3.3
SOFTWARE: Chapter 3.4
LOW VOLTAGE: Chapter 4
HIGH VOLTAGE: Chapter 5
SLOW CONTROL: Chapter 6
EMC: Chapter 7
ALICE TRACKING DIMUON SYSTEM:
ELECTRONICS & SOFTWARE
Translator
Board.
LOW VOLTAGE
EMC
10 Meter max
Ribbon cable
READ OUT.
CROCUS Crate
Up to 50 PATCH BUS connected.
FRT
DAQ
Optical link:
DDL
100 meter.
PC
CRT
SOFTWARE
Ribbon cable
40 meter
TCI
One crate for all
CROCUS.
FFT FTD
Link to download:
Pedestals.
DSP code.
From CTP
Trigger information:
L0, L1…..
ETHERNET:
- Monitoring.
- Stand alone DAQ.
- Test configuration.
fig 1:
2000 evts/s for the high intensity Ca beams.
- 142 -
The choice has been done to use DSP AD21160M (Digital
Signal Processor) farms to achieve the data readout coming
from the FEE. These DSPs are gathered in « clusters » in 20
specific crates called CROCUS (Cluster Read Out
Concentrator Unit System). Each crate is composed of 5
cards called « frontal » directly connected to the Patch
buses by ribbon cables and of a concentrator card which
collects the data coming from all the frontal cards then,
after, formatting, transmits them to the SIU (Source
Interface Unit) which will achieve the transmission towards
the DDL (Detector Data Link) (fig 1). This modularity
provides a high readout speed and minimizes the

General & technical Departments
consequences of a malfunctioning of an element. Moreover,
the use of all these DSPs permits the buffering of events at
different levels in the readout chain.
Each CROCUS crate has many functions :
- it picks up the detectors data, it concentrates them, it
sends them to the DAQ
- it generates the Front-end control signals and send
them to the front-end through buses
- it picks up trigger signals from dispatching crate and it
broadcasts them to the Front-end electronics
- It generates calibration signals, it sends them to the
detectors, and it processes the calibration data and it
sends them to the DAQ
- It detects failures on the read out chain
The production of the 22 crates is foreseen for 2006.
The very complex software design is in progress
All the CROCUS crates are close to the detector (less than
10 meters) to insure a good efficiency of the data
acquisition through 8 bits/ 20Mo/s linkport. The crate itself
is a specific one VME 6U 9T, amagnetic aluminum made,
very compact to be easily integrated on the detector.
The CROCUS architecture concentrates data with the
following scheme :
- each CROCUS frontal board (CROCUS_FRT) receives
data from 10 buses and it concentrates them within 2
front-end DSP.
- All the front-end DSP (10 for a CROCUS crate) are
connected through the back plane (CROCUS_back) to
2 DSP called concentrators located. Each connection is
done with a linkport.
- The concentrator DSP are located on a concentrator
board called CROCUS_CRT.
- A master DSP located on CROCUS_CRT gathers all
the data via a parallel bus 320MB/s and sends them
through a Xilinx FPGA to the SIU unit
- The SIU unit transmits data to ALICE DAQ with an
optical fiber.
References
Fig 2 : CROCUS crate prototype
CROCUS_FRT, CROCUS_CRT, CROCUS_Back boards
are designed. Their integration in the specific crate is in
progress.
[1] The electronics of ALICE dimuon tracking chamber PRR
(2003)
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General & technical departments
The ASIIC developmentt actti ivitti
ies off tthe Electtrroni
ics Grroup
IPNO Participants : J.-C. Cuzon, S. Drouet, P. Edelbruck, E. Wanlin
Les activités de développements d’ASICS du Service d’Electronique Physique
Les détecteurs développés dans le domaine de la physique nucléaire embarquent aujourd’hui une instrumentation
de plus en plus complexe qui peut parfois comporter plusieurs millions de voies de mesure. Les niveaux de
précision requis, les volumes de données, la complexité des traitements effectués en ligne et les vitesses de
transfert conduisent fréquemment à abandonner les technologies d’électronique traditionnelle (discrète) et à
recourir aux techniques d’intégration sur silicium. Le Service d’Electronique Physique de l’Institut est engagé dans
cette voie depuis de nombreuses années et possède à son actif des réalisations importantes. On peut citer un
circuit de mesure de temps (TDC) destiné à la spectrométrie de masse, une chaîne de mesure pour les détecteurs
au silicium développée en collaboration avec le CEA et dernièrement une mémoire analogique rapide destinée à la
numérisation de signaux à très grandes vitesses. Le savoir-faire acquis par le groupe dans le domaine du
développement d’ASIC est aujourd’hui significatif et les outils informatiques disponibles permettent d’aborder le
développement de circuits analogiques-numériques complexes.
The complexity of the electronic equipment embedded in
nuclear physics detectors is becoming quite complex in
terms of technical specifications but also in terms of
channel count. A detector may comprise several millions of
electronic channels. The required precision level, the
volume of data and the complexity of the processing
performed online often leads to move from traditional
discrete technology to integrated solutions. The Electronics
Group of the Institute has started integrating designs many
years ago and several components have been developed.
CRT-C DST-9
I) was instrumented in the early 90’s with discrete
electronics. The second generation detector had several
hundreds of channels and clearly required an integrated
solution. A collaboration team was set up between IPN and
CEA for the design of an ASIC. The aim was to come up
with a chip performing timing and energy measurements
for 16 channels in a single chip (preamplifier, trigger,
shaper, time to analog converter and data read-out). The
preamplifier, the energy section and the logic interfaces
were designed at IPN and the timing and the multiplexing
modules at CEA.
The first achievement was a chipset aimed to mass
spectroscopy. The issue at this time (mid 90’s) was more of
a technical nature. The requirement was to measure time
intervals with a resolution better than 0.25 ns and a very
high repetition rate (multi-hit). Less than 20 ns may have
elapsed between two successive events. These features
were absolutely not achievable with commercial
components and have led to the design of two original
ASICs. The development has been performed using a
bipolar technology from the French silicon founder
Thomson. It was a success and the chips have been used in
a wide range of instrument during 10 years. They represent
the heart of CTN, a module aimed to mass spectroscopy,
now in use in many laboratories worldwide, as well as
COMET, a general purpose acquisition board used at
Tandem and CERN. They have also been implemented in
TOHR, a high resolution instrument for nuclear biology
research and recently in G0, an experiment in hadronic
physics (TJNAF-USA).
MUST
Many experiments in nuclear physics use detectors
sensitive to charged particles. Semi-conductor devices are
very well suited for this purpose and allow for a precise
measurement of energy, time and position. Position
measurements are using matrix of silicon detectors with
high channel counts. The first detector of this kind (MUST
- 144 -
MAR
View of the ASIC MAR
Another field rapidly developing in nuclear instrumentation
is the digital pulse shape analysis of signals issued by

General & technical departments
detectors of many kinds. These techniques can be used for
the localization of an interaction within a crystal
(Germanium) and for the mass over charge discrimination
of the incoming particle (silicon or scintillators). Off the
shelf fast flash ADCs can be used directly when the signals
are reasonably slow. With faster signals, the analog to
digital conversion cannot be performed directly. One way
to overcome this difficulty is to sample and store the fast
signal in a high speed analog memory (pipeline) and to
“replay” the portion of interest at a lower rate, allowing for
the use of a conventional flash ADC. The technique is
called FISO (Fast In - Slow Out). Although such methods
are now well known, no component is available on the
market place. The technique is clearly relevant for the
AZ4π R&D program and the design of such an analog
pipeline was decided.
The recording device is composed of a matrix of 1240
analog storage cells. Each cell is written in turn, with a time
interval of 0.5 ns. The matrix is handled as a ring buffer,
i.e. writing is performed continuously, overwriting the
older cells, until the process is stopped by a trigger signal.
The content is then frozen and the stored voltages can be
read out through a read bus.
successfully tested. 25 units have been packaged and will
been used to build up a first set of prototype boards for the
actual detector. However, a few flaws have been detected
and corrections will be performed. A new prototype will be
submitted to the founder at the beginning of 2006
The fast amplifier
Several building blocks had to be especially designed for
this application:
- The storage cell itself, composed of a capacitor
associated to very accurate switching devices
- The delay-locked-loop, an element delivering the 0.5
ns time interval
- The read and write amplifiers, with a bandwidth as
large as 350 MHz and high slew rate
- The logic of the whole system.
The building blocks were designed in such a way that they
can be reused later, even for a different application.
Furthermore, two of them were made available to the entire
IN2P3 community through the special “club 035” structure
started in 2004.
The amplifier test chip
Perspectives
The delay-locked-loop
The blocks were first manufactured as single elements in
special test chips and tested. The entire design has then
been assembled and the complete chip manufactured
beginning of 2005. The circuit was functional and has been
The Department of Electronics has now built up a valuable
experience in ASIC design. Skilled engineers doted with
powerful CAD tools are available within the Institute.
Numerous physics project can and will use these techniques
in the future. They will benefits in both the increase of the
performance level (precision, energy and timing
resolutions) and the complexity level : complex signal
processing over millions of channels.
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General & technical departments
MAR :: An asic fforr tthe ffastt digittal
lizatti
ion off currrrentt signals
IPNO Participation : J.-C. Cuzon, S. Drouet, P. Edelbrück, L. Leterrier, E. Wanlin
MAR : un asic pour la numérisation rapide des signaux de courant
Développé il a 4 ans, le préamplificateur à grande vitesse PACI offre une image précise du processus de collection
de charge d'un détecteur de silicium. Ce signal peut être employé pour la discrimination en Masse/Energie dans ce
type détecteur, en utilisant des techniques de filtrages numériques. Comme aucun composant du commerce ne
s’adapte à nos contraintes, nous avons décidé de concevoir un circuit intégré (asic) d’une mémoire analogique
(MAR) qui échantillonne le signal à très grande vitesse (jusqu'à 2 GSPS) avec la possibilité d’être lue à une vitesse
inférieure (50 MSPS) en employant un ADC du commerce. La profondeur de stockage de cette mémoire est
d’environ 1240 échantillons, avec une vitesse d'écriture réglable (de 100MSPS jusqu’à 2GSPS). Après l’étape de la
conception et du dessin physique, le layout a été envoyé chez le fondeur (AMS) en décembre 2004 et nous avons
reçu 25 puces encapsulées en mars 2005. Actuellement nous sommes en train de tester les performances et
fonctionnalités de cet asic MAR dans le but de réaliser une carte d’acquisition rapide.
Introduction
Four years ago, the Electronics group developed a new
version of charge preamplifier called PACI having an
additional output of which the signal is a faithful
representation of the current pulse. The knowledge of the
shape of this pulse makes possible to obtain additional
information (A, Z...) in order to improve discrimination.
Accordingly, the electronics group is designing and
realizing a fast acquisition system allowing to digitalize the
output current signal of a preamplifier PACI. These current
signals have the following time characteristics: minimum
rise time of 2-3ns, duration of the impulse of few 10ns to
100ns.
Considering the minimum rise time, the digitalization
system must be very fast, more than 1GSPS (giga samples
per second). Knowing that the very fast converters (>
1GSPS) available in the market do not correspond to our
application (too high dissipation, high price, 8 bits of
resolution), the SEP decided to develop a ASIC which
memorize the current signal at 2GSPS in an analog way.
on one of the DLL, this one is lower than 10ps rms. The
average value of one delay is 502ps.
When the analog levels of input current signal are
memorized in the asic, all the samples are sent to an analogto-digital
converter with a sampling frequency of 50MSPS
and with 12bits resolution. The digitized samples are then
processed by a FPGA realizing a digital processing of the
data.
The diagram below represents the test bench which permits
to characterize the MAR asic.
Presentation of the asic MAR
This ASIC called MAR (Fast Analog Memory = Mémoire
Analogique Rapide) is based on an analog pipeline structure
storing the samples in an analog circular buffer. The aim of
this memory is to memorize in an analog way the current
signal coming from the detector via the PACI preamplifier.
This analog signal is sampled at 500ps (2GSPS) by the
1239 memorizing cells made of capacitors and MOS
switches. Thus, this memory can store a 619.5ns signal
when the time base is 500ps.
In the asic, the 1239 cells are placed in matrix form : 59
lines by 21 columns. Thus, each line contains 21 memory
cells. This dimension was not taken randomly : thanks to
this one, the asic can sample the signal with various time
Fig. 2 : Photo of the test bench with the asic MAR
bases without having time distortion. The following time
bases are available : 500ps, 1ns, 2ns, 5ns and 10ns.
Features of the asic MAR
It is important to note that each line is made up of 21 • Built in 0.35µm CMOS technology by AMS
memory cells and a DLL (Delay Locked Loop). These 59 • Area : 23mm²
DLLs give all the precision of the moment of sampling. On • Supply voltage : 3.3V ; Power : 800mW
the first version of the asic, jitter measurements were made • Input span : 2Vpp
- 146 -
C DET
C F
PACI
Sortie
courant
Sortie
énergie
Trig
Mémoire
Analogique
Rapide
ASIC "MAR"
Convertisseur
Analogique-Numérique
50MHz / 12bits
Contrôleur
d'Acquisition
Mémorisation
Données
Gestion USB
Carte d'acquisition commandée par un module USB
USB
Traitement
Données
Visualisation
Fig. 1 : Functional diagram of the test bench of the asic
PC

General & technical departments
• Input bandwidth : 350MHz
• Expected S/N ratio: 72dB
• Programmable time bases (in GSPS) : 2, 1, 0.5,
0.2, 0.1
• 1239 memory cells (matrix of 21x59 cells)
• Memory depth : from 619.5ns to 12.39µs (in
function of the selected time base)
• Read time (Sending of all the analog samples to
the ADC) : 25µs
Asic status
All the analog part of this ASIC was designed, simulated,
optimized and drawing by the SEP.
All the digital part allowing the control of the analog
pipeline was designed by the SEP and the layout (drawing)
was made at Strasbourg thanks to the help of A. Himmi
(Laboratory IReS/IN2P3).
The first version of the asic was sent to the AMS foundry at
the beginning of December 2004, and we received 25 chips
in the middle of march 2005.
The design and the realization of the asic test bench was
performed in parallel with the foundry of the asic.
For few weeks, the SEP has tested the asic (cf. Fig.2), and
for a first prototype, good results appeared. Below, we can
see some sampling results (made by MAR):
Fig. 3 : Sinusoidal signal with a 20MHz frequency and an
amplitude 800mVpp
Some mistakes appeared during the test. Thus, some
correction of the layout will be done, and a new version of
the asic will be sent to the AMS foundry in the first quarter
of 2006. So, the new version will be tested in mid-2006.
It is important to note that the first version of the asic
MAR works and thus, we will use it in a demonstration
board for AZ4π experiment despite its imperfections.
Future objective
The final goal is to realize a fast acquisition board :
C DET
C F
PACI
Current
Output
Charge
Output
Analog-to-Digital
Converter
Fast Analog
Memory
MAR
AD9235
Sampling Board
Acquisition controller
+
Data storage
+
Communication controller
FPGA and DSP
Analog-to-Digital
Converter
AD9235
Fig. 5: Acquisition board for AZ4π
GBit Link to
DAQ
Trigger
&
Timing
This board will meet the following characteristics :
‣ Compactness (a few cm²) for the integration close to
the detectors (a few thousands channels must be
equipped).
‣ low thermal dissipation.
‣ Modularity.
‣ One energy channel.
‣ One channel for the process of the current signal
(shape analysis).
So, the first objective is to correct the layout for the second
version of MAR (mid-2006).
The second objective is to realize a fast acquisition system
for the AZ4π R&D program, with the collaboration of LPC
Caen and INFN Florence. This system will integrate, of
course, the asic "MAR", and will be able to do recognitions
of the current signals coming from the preamplifier PACI.
For the first version of this system, we will use the first
version of the asic MAR. The first version of this board will
be available in the beginning of 2006.
Fig. 4 : Sinusoidal signal with a 100MHz frequency and an
amplitude 650mVpp
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General & technical department
The Frrontt End Electtrroni
ics off tthe AGATA dettecttorr
IPNO Participation : P. Edelbruck, X. Grave, C. Huss, C. Oziol, S. Royer.
Collaboration : CCLRC, CSNSM, INFN, IReS.
L’électronique de Front-End du détecteur AGATA
AGATA est un spectromètre gamma destiné aux expériences de physique des noyaux exotiques. Il comprend 180
cristaux de germanium de gros volume fonctionnant à basse température. Chaque cristal est segmenté en 36
sections dont les électrodes sont lues par des préamplificateurs à faible bruit embarqués. Ce détecteur apportera,
par rapport à ses prédécesseurs une grande amélioration en efficacité (zones mortes réduites) et en résolution. Il
bénéficiera, au niveau de son électronique de deux innovations techniques majeures : un traitement entièrement
numérique des signaux, associé à une méthode de localisation des interactions basée sur l’analyse des impulsions
de collection de charge. Chacune des 7000 voies d’électronique sera munie d’un convertisseur Analogique-
Numérique à grande vitesse et grande résolution (Flash ADC) associé à une électronique d’acquisition fortement
intégrée. C’est cette électronique qui est en cours de développement à l’IPN, en collaboration étroite avec le
CSNSM voisin. Ce dernier fournira les cartes de traitement de premier niveau (1250 unités) et l’IPN l’infrastructure
bâtie sur le nouveau standard de télécommunication ATCA (360 cartes portées par 30 châssis).
AGATA is a gamma ray detector aimed to high resolution γ
-ray spectroscopy with exotic beams. Despite its large size,
it is designed to be “portable” and will be used in several
nuclear physics facilities in Europe. The detector is made of
180 crystals of high purity germanium. Each crystal is
segmented into 36 volumes, each of which bearing one
electrode, also called segment, read by a high resolution
preamplifier. The detector will provide significant
improvements over its predecessors in terms of efficiency
(reduced dead zones) and resolution. It will benefit from
two major technical innovations: all signal processing will
be entirely digital and new localisation algorithms will be
performed on the charge signals, allowing for
unprecedented spatial precision. To achieve these goals,
each of the 7000 channels will be read out by a high speed
analog to digital converter associated to a strongly
integrated digital electronics. This electronics is currently
being developed between IPN and the neighbour lab
CSNSM. The later is providing the first level local level
mezzanine boards (1250 units) while IPN is designing the
infrastructure, based on the new ATCA telecom standard
(360 boards located in 30 crates).
Computing Architecture. This is a new hardware standard
originally designed for telecommunication systems,
featuring very high bandwidth (potentially hundreds of
Gbyte/s). One crate can accommodate up to 16 large
boards, with a form factor well suited to carry the projected
pre-processing modules. Communication between the
chassis and the external world is performed by one or two
switching boards locally connected to the carriers through
high speed serial links located on the backplane. One single
link offers up to 10 Gbit/s of data rate. The actual
communication protocol is not defined by the standard and
remains open for a future choice. The first demonstrator
will use the well known Gigabit Ethernet standard while the
final version will use PCI-express or Infiniband offering
even more bandwidth.
14U
1,5U
8U
3 X 2 Carriers =
1 cluster
15
13
11 9 7 5 3
1
2
3 X 2 Carriers =
1 cluster
4
6 8 10 12 14 16
SWITCH
GbE
ou
PCIexpress
CPU
(option)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
The 36 fold segmented germanium crystal
The ATCA standard
The AGATA throughput is currently estimated to 380
Mbyte/s per crystal i.e. 2.2 Gbyte/s for the 6 crystal filling
in one crate. A breakthrough was really required to cope
with such a data rate. The solution was found with ATCA.
The acronym stands for Advanced Telecommunications
- 148 -
4,5U
23’’
One chassis bearing the electronics of 6 crystals
System architecture
The signals issued by the crystals are first digitized in the
vicinity of the detectors by an ensemble of ADC (14 bit -
100 Msample/s) developed by IReS in Strasbourg. The high
speed digital stream is transported to the local level

General & technical department
processing electronics through optical fibres at the rate of 2
Gbit/s. One set of fibres is handling 6 electrodes, 6 sets
being required for one crystal, plus one for the central
contact. Each fibre feeds one mezzanine card where the
digital stream is rebuilt for processing using high speed
deserializers (SERDES). Field Programmable Gate Arrays
(FPGA) perform in real time the calculation of the energy
of physical events (digital shaping) and the recording of the
signal shape, just like a digital oscilloscope. Another type
of mezzanine board (Global Trigger System) designed in
Padova (INFN) provides an accurate clock to the whole
system. It also delivers the “date” of all physical events
with a resolution of 10 ns (Time Stamping).
1 crystal
6 Segments
Digitiser
6 Segments
Digitiser
Core
Digitiser
6 Segments
Digitiser
6 Segments
Digitiser
6 Segments
Digitiser
6 Segments
Digitiser
Central
trigger
GTS
CORE
SEG
SEG
SEG
SEG
SEG
SEG
ATCA
DAC
ATCA
DAC
Master
Slave
The electronics of one crystal
Slow
control
PSA
Or PrePSA
Power
management
The pre-processing boards
The pre-processing boards are built around state of the art
FPGA of the Virtex-II pro family. Two chips are required
for six channels. Each chip bears the deserialsers, one
power-PC processor and several millions of programmable
logic gates performing all the digital processing in real
time. The boards communicate with the central control
system through Ethernet links taken over from the carrier
boards.
Data acquisition
Clock
TCLK port
Slow control
OSC LOC
CY
2DP3120
The carrier boards
JTAG connect.
JTAG
JTAG
SWITCH
AS91L1006
FPGA
TCLK OSC LOC
RevMII
JTAG
32 bits 100Mhz
CPU TRACE
LSA connect.
JTAG
FIFO
CPU serial
EEPROM
Config CPU
Switch
10/100
ZL50407
DATA
FIFO Acquisition
FPGA
FIFO Carrier
XC2VP40/50
FIFO
JTAG
CTRL
AS91L1001
The carrier board
32 bits
CPU
SRAM
256Ko
OSC LOC
RevMII
32 bits
100ME Base
PHY Fabric
MII
C
P
U
MOBILE
SDRAM
128Mo
Micron
selectMap
EEPROM
Config
JTAG DAFC
TCLK PORT
HUB1
HUB2
PCI Express
ou GbE
I2C thermal
And power
control
POWER
3.3V 2.5V
1,2V 1.5V 1.8V
The role of the carrier boards is to provide an infrastructure
to the processing mezzanine cards. Each detector will
necessitate two carriers holding six segment mezzanines,
one central contact mezzanine and one GTS card. The first
facility offered by the carrier is of a mechanical nature. One
carrier card will house four mezzanines built in the
standard PMC form factor. The connexions to the detectors,
to the ADC system and to the central trigger will be
performed through the front panel with optic fibre
connectors. The carrier board will also generate the
voltages required by the various components. Up to 200 W
of power will be converted into 6 different low voltages
from the unique 48 V source provided by the ATCA
backplane.
Two large FPGA will handle the data acquisition process
itself. Synchronisation signals will be received from the
GTS board and distributed to all mezzanines. Trigger
requests will be gathered from the central contact and sent
to GTS. Trigger commands will then be dispatched to all
cards. When the reading process is completed on each
mezzanine (energy calculation, signal storage etc.) the
carrier board will collect the data from all modules, build
the event package and send it to the central DAQ through
the backplane and the switch boards.
Last but not least, the carrier will handle all the “slow
control” issues, ranging from basic house keeping like
power and temperature management, software download, to
physics parameter handling and online calibration
procedures. As the total number of FPGA in the system
will be very high (several thousands), all possible
maintenance operation like updating the hardware codes
(VHDL) will be feasible from the remote central control
system without any manual intervention on the boards. All
slow control communication will be performed through
standard Ethernet links using the TCP/IP protocol, making
remote control versatile and portable.
Pulse shape analysis
The 30 ATCA chassis will communicate with a large
processor farm which will perform the in-line analysis of
all the channels in order to extract two important data :
- The geometrical location of the interaction within the
crystal. This information will permit a precise
correction of the Doppler Effect affecting the energy
measurement, leading to a resolution improvement of
an order of magnitude over existing detectors.
- In the case of a Compton cascade, determine the
position of each photon belonging to the event and
calculate the total energy as well as the angle of the
original photon.
The next future
Building and testing the electronics will take three steps :
one single detector will be equipped and tested mid 2006 in
Orsay. A demonstrator made of a large set of 15 detectors
will then be constructed and used for real physics
experiments in 2007. The complete detector with 180
crystals will be ready by 2010.
- 149 -

General & technical departments
Electtrroni
ics fforr MUST2 ((MUrr à Sttrri ip))
IPNO Participation : J.-P. Baronick, D. Beaumel, P. Edelbruck, G. Guerin, P. Guilland, D. Lalande, L.
Lavergne, L. Leterrier, V. Le Ven, A. Mongaillard, D. Rougier, S. Royer, S. Tanguy, M. Vilmay, E. Wanlin
Collaboration : GANIL, CEA/DAPNIA.
MUST2 est un télescope ∆E-E de seconde génération constitué d’un détecteur Si à 256 pistes double face suivi de
deux détecteurs Si(Li) segmentés en 8 secteurs et de seize cristaux de CsI. Les détecteurs, l’électronique front end
et la mécanique ont été pris en charge par le service détecteurs de la DR, le SEP et le SRM. L’électronique front
end est réalisée autour d’un composant intégré full custom (MATE3), conçu en collaboration avec le CEA/DAPNIA.
Pour l’électronique d’acquisition, elle a été conçue par le GANIL en standard VXI taille C. Actuellement, la
production d’un ensemble de quatre télescopes est lancée et sera achevée en janvier 2006. Le reste de la
production sera réalisé courant 2006. Les premières résolutions en énergies obtenues avec le détecteur Si à strips
sont de l’ordre de 40keV avec une source alpha 3 pics et de 30keV au générateur d’impulsion.
MUST II is a charged particle detector of second generation
developed in collaboration with GANIL, CEA/DAPNIA
and IPN. Each telescope (Fig 1) consists of a double-sided
Silicon strips (Si strips) detector, followed by two Silicon
Lithium (Si(Li)) detectors and sixteen Caesium Iodide (CsI)
scintillators with photodiode read-out. The Si strips detector
has128 strips on each side and the expected energy and time
resolution are 50keV and 250ps for 5.48MeV alpha. Each
Si(Li) detector is divided into 8 segments with the 120keV
desired energy resolution. For the CsI, the requested energy
resolution is 5% for 5.48MeV alpha.
All mechanics has been designed by SRM. In particular,
this mechanics is composed of the cooling system allowing
to drain the heat of electronic devices of outside the vacuum
chamber in order to hold a constant low temperature.
Si (Li)
Si (Strips)
CsI
Kapton
Front end electronics
The front end electronics, realized by SEP, is located close
to the rear of each telescope and consists of two electronic
boards called MUFEEX3 (MUst Front End Electronics) and
MUFEEY3. The links between Si strips detectors and
electronic boards are made via Kapton flexible circuits.
Above, the top and bottom views of the MUFEEX3 board
processing 128 signals from the junction side of Si strips
detector, as well as the 16 channels of the Si(Li) detectors.
MUFEEX3 and MUFEEY3 boards are nearly the same.
Apart from MUFEEY3 which processes 128 signals from
the ohmic side of Si strips detector and 16 channels from
photodiodes.
Each MUFEE bears 9 MATE3 ASICs (Application Specific
Integrated Circuits), each processing 16 channels in energy
and time. These energy and time information are carried on
2 analogue lines per board, read in current differential mode
through twisted pair to the external VXI crate. The MATE3
are connected in daisy chain and read one after the other.
The readout time for 544 information is 80µs.
In order to have a good immunity against the
electromagnetic perturbations, all readout signals are
transmitted in LVDS (Low Voltage Differential Signal).
The slow control, assured via the I²C industrial protocol,
allows in particular the configuration of the ASICs, the
temperature monitoring, the test signal injection, the
multiplexing of inspection channels, the board
identification and the memorization of experiment
parameters.
On each MUFEE, one pulse generator drive each analogue
test input of each MATE3, which allows to check the good
functionality of all ASICs and to calibrate electronics
channel.
MATE3 (Must Asic for Time and Energy)
It has been realized in collaboration with the CEA/DAPNIA
from Saclay : SEP has developed the charge sensitive
preamplifier, the energy channel and the logic I2C
interface; CEA has taken responsibility for the timing
energy and other blocks explained later and for the final
assembly. The ASIC technology is the 0.8μm BICMOS
from AMS. MATE3 has 16 channels and delivers three
types of analogue information for each channel: time of
flight and energy loss of the detected particle and value of
DC leakage current. MATE3 also gives a trigger logic
signal corresponding to the cross over of an adjustable
threshold. The slow control of the ASIC is assured via the
I2C industrial protocol.
- 150 -

General & technical departments
Architecture
The block diagram of one MATE channel is shown
hereafter:
ini
idf
idf
ininj
cf1
Idf
CSA
cf0
¼Cf
Rf
selFiltre
1us/3us
Filtre & Ampli
Filtre &
Ampli
hold
Track&Hold
TEMPS
+ discri - TAC
resetCSA seuils
requêtei stop
DAC 8 bits
Requete j
Canali
REQUÊTE
VIC
DATA
One channel consists in three main blocks : A charge
sensitive preamplifier, the energy block, and the time and
decision block.
MATE3 must be able to accept current signals coming not
only from both sides of the Si strip detector, but also from
SiLi and CsI detectors. This means that each channel can
process both signal polarities, from the charge sensitive
preamplifier to the energy and time blocks. Furthermore,
the charge sensitive preamplifier gain and the filter peaking
time are programmable to suit various kind of detectors and
particles.
Charge sensitive preamplifier
The architecture is a single ended folded cascade amplifier,
bipolar, using MOS and bipolar transistors. The input
transistor is a wide PMOS of 8500μm/1.2μm
(gm=28.4mS). The rise time of the preamplifier is 10ns.
A set of four integration capacitors programmable via two
slow control bits is used to match the desired gain
according to the selected detector.
The maximum energies to be accepted by the charge
sensitive preamplifier and energy block are +/-45MeV,
225MeV and 200MeV for the Si strips, SiLi and CsI
detectors respectively.
Energy channel
This block is composed of a shaper and a track and hold.
The shaper consists of a CR-RC filter, with respectively 1
and 3μs of peaking time, selectable by slow control, for the
Si strips and SiLi/CsI detectors.
Then, the amplitude of the signal is memorized via a track
and hold stage on the rise time of the HOLD signal coming
from MUVI. In read out mode, this memorized signal is
sent to a Voltage to Current Converter (VIC) whose transfer
gain is +/-2mA/V.
Timing and decision channel
This channel has two main objectives : determine quickly
whether the channel has triggered or not and measure the
time of flight of the particle.
The first section is a fast CR 2 -RC filter with a peaking time
of 22ns; it has a differential structure, thus providing
immunity against parasitic coupling and reducing jitter to
achieve a good time resolution. The differential outputs of
this shaper, then, pass through a leading edge discriminator,
OU
x16
ENERGIE
COURANT
in which the threshold voltage is set by an internal 8 bits
programmable DAC.
The discriminator output gives the start signal to the time to
amplitude converter (TAC) as well as the « REQUETE »
signal which is ‘or wired’ with the other fifteen channels of
MATE3. The intrinsic time resolution of the TAC is 18ps
FWHM. The TAC is stopped by an external signal “STOP”
coming from MUVI.
In read out mode, the time information is sent to a Voltage
to Current Converter.
The TAC has two programmable time ranges: 0ns/300ns
and 0ns/600ns.
Power consumption, layout and package
The power consumption of the chip is 447mW. The layout
is shown hereafter; the area is 41mm2
(6.438*6mm.368mm). MATE is packaged in a ceramic 64
pins TQFP64L.
Inpac1
Inpac16
Complete telescope system
The GANIL developed a VXI-C standard board, called
MUVI (MUst in VXI), assuring the slow control, data
coding, digital processing and data memorization for four
telescopes. The management of trigger signals is performed
by the GMT module.
The communication between MUFEE and MUVI boards is
carried in the eight meters transmission line.
The ensemble of front end electronics is supplied by several
CAEN power supply modules located in SY1527 system.
Châssis VXI
MUVI (VXI taille C)
Mémorisation
&
Traitement
&
contrôle
host
Interface VXI
Mise en forme
4 bus analog
& codage
Signaux cont
Slow control
Bus I2C
Trigger local
Trigger externe
GMT
1 bus analog
bus I2C 1 bus analog
signaux cont.
1 MATE2
8 MATE2
MUFEE Y
INTERCSI
128 strips en Y
16 pads
128 strips en X
8 MATE2 1 MATE2
1 bus analog
signaux cont. bus I2C 1 bus analog
Détecteur Si strips
Détecteur Si(Li)
16 pads
Détecteur CsI
MUFEE X
- 151 -