Effect of Ground Return Path on Timing Accuracy

Gert Hohenwarter
GateWave Northern
<strong>Effect</strong> <strong>of</strong> ground return path on
timing accuracy
Company
Logo
June 8-11, 8
2008
San Diego, CA USA

Objective
• Review problem <strong>of</strong> ground path
• Identification <strong>of</strong> trouble spots
• Assessment <strong>of</strong> individual impact
• Demonstrate significance
• Summary
June 8 to 11, 2008
IEEE SW Test Workshop 2

Approach
• Examine complete signal path in a probecard
• Develop models (FEA, SPICE)
• Use models to evaluate impact <strong>of</strong> changes
• Provide select measurement results to
corroborate models
June 8 to 11, 2008
IEEE SW Test Workshop 3

Problem
• Signal in transmission line needs a return path
• This path must be located physically close to the signal
• Disruptions/detours add inductance and therefore delay
June 8 to 11, 2008
IEEE SW Test Workshop 4

Probe card signal path
June 8 to 11, 2008
IEEE SW Test Workshop 5

Probe card signal path
• The signal path in the probecard begins at the
perimeter with a tester connection and ends at
the probe tip with a connection to the DUT
Alongside the signal path a ground return must be provided
June 8 to 11, 2008
IEEE SW Test Workshop 6

Follow the signal…..
• Timing verification begins at the tester
connection with a time domain reflectometer
and a test probe…..
June 8 to 11, 2008
IEEE SW Test Workshop 7

…through the probe…..
• Common probes <strong>of</strong>ten have a fixed signal
contact and movable connection at ground:
June 8 to 11, 2008
IEEE SW Test Workshop 8

Consequences
• <strong>Ground</strong> path inductance changes
• Signal path capacitance changes
June 8 to 11, 2008
IEEE SW Test Workshop 9

Consequences
• <strong>Ground</strong> path inductance changes
• Signal path capacitance changes
• Delay changes
FEA analysis
dLprobe [nH]
2
1
0
‐1
‐2
‐3
‐50 0 50
Angle
dT [ps]
60
50
40
30
20
10
0
SPICE model
dT [ps]
0 2 4 6
Lg [nH]
June 8 to 11, 2008
IEEE SW Test Workshop 10

Verification
• Measurement at actual probecard PCB
• At first glance everything is fine….
Multiple TDR
Multiple TDR
rho
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
0 1 2 3 4
t [ns]
rho
1.000
0.800
0.600
0.400
0.200
0.000
3 3.5
t [ns]
straight
long inline
short inline
ortho 30
gnd2
gnd3
gnd4
June 8 to 11, 2008
IEEE SW Test Workshop 11

Delay extraction
• When processing the data, differences become noticeable
10.0
8.0
Delay variations
2.0
0.0
Delay variations
6.0
-2.0
dt [ps]
4.0
2.0
0.0
-2.0
-4.0
-6.0
-8.0
-10.0
meas 1 meas 2 meas 3 meas 4 meas 5
dt [ps]
-4.0
-6.0
-8.0
-10.0
-12.0
-14.0
long inline
short inline
ortho 30
gnd2
Condition
gnd3
gnd4
least favorable
Measurement to measurement
For different probe positions
(probe straight)
dT = 5 ps
dT tot= 5 ps
dT counter: ->
(average, not max. dT)
June 8 to 11, 2008
IEEE SW Test Workshop 12

Follow the signal…..
• <strong>Ground</strong> via selection (only one ground via present for each case):
dL [nH]
dL for 0.5 mm pitch
0.4
0.3
0.2
0.1
0
near side side far
Inductance difference for 0.5 mm pitch
dT = 3 ps
dT tot= 8 ps
June 8 to 11, 2008
IEEE SW Test Workshop 13

Follow the signal…..
• The signal travels into the PCB through a
connector and returns through an array <strong>of</strong> vias:
Disorganized
Organized
dT = 10 ps
dT tot= 18 ps
June 8 to 11, 2008
IEEE SW Test Workshop 14

Follow the signal…..
• PCB via position (vias must be provided near level shifts):
dT [ps]
dT [ps]
12
10
8
6
4
2
0
0 50 100
dy [mils]
Inductance change as a function
<strong>of</strong> lateral via position
dT = 5 ps
dT tot= 23 ps
June 8 to 11, 2008
IEEE SW Test Workshop 15

Follow the signal…..
• <strong>Ground</strong> planes are disrupted in LGA/interposer area
Inductance per unit length changes
If traces get close to via antipads,
capacitance per unit length changes,
too
Example (inductance only):
Uniform array <strong>of</strong> 1mm pitch vias
<strong>Ground</strong> path inductance changes by
12% for a 40 mm long path
dT = 16 ps
dT tot= 39 ps
June 8 to 11, 2008
IEEE SW Test Workshop 16

Follow the signal…..
• <strong>Ground</strong> via positions in the interposer contact array
5
4
3
2
1
0
Inductance [nH]
1 2 3 4
# gnds
Inductance as a function <strong>of</strong> via distance from signal and number <strong>of</strong>
ground vias
dT = 10 ps
dT tot= 49 ps
0.5
1
1.5
2
mm
June 8 to 11, 2008
IEEE SW Test Workshop 17

Follow the signal…..
Delay change as a result <strong>of</strong> branch imbalance in ground path
150
dT [ps]
100
50
0
-50
-100
dT top 10k
dT bot 10k
dT top 50
dT bot 50
-150
0 0.5 1 1.5 2
Lg [nH]
Different load conditions result in
different delay changes
dT = 30 ps
dT tot= 79 ps
June 8 to 11, 2008
IEEE SW Test Workshop 18

….to the DUT
Delay change as a result <strong>of</strong> grounding configuration at the DUT
Dense ground
With typical dimensions assumed the
inductance difference for the two
different configurations is 0.88 nH
Sparse ground
dT = 5 ps
dT tot= 84 ps
June 8 to 11, 2008
IEEE SW Test Workshop 19

Overall changes
Graphic representation <strong>of</strong> relative change as a function <strong>of</strong>
where change occurs
90
80
70
60
50
40
30
20
10
0
ps
Delay as a function <strong>of</strong> location
meas
via pos
TR vias
Sum
Individual
trace vias
interposer vias
interposer gp holes
Space TR - SDR
probes/DUT
Comment:
Line length matching to
within 20 mils results in
an inaccuracy <strong>of</strong> 3.5 ps
June 8 to 11, 2008
IEEE SW Test Workshop 20

The impact <strong>of</strong> location
Delay change as a result <strong>of</strong> inductance change at
different locations along the signal path
Approximate equivalent circuit <strong>of</strong> signal path
June 8 to 11, 2008
IEEE SW Test Workshop 21

The impact <strong>of</strong> location
Delay change as a result <strong>of</strong> inductance change at
different locations along the signal path
dt [ps]
dT at different positions (50%)
50
40
30
20
10
0
1n
2n
3n
1 2 Pos # 3 4
Signal at DUT (SPICE simulation)
Delay change
June 8 to 11, 2008
IEEE SW Test Workshop 22

Waveform change
Wave form changes as a result <strong>of</strong> inductance change
dT at different positions (85%)
50
0
dt [ps]
-50
-100
-150
1n
2n
3n
1 2 Pos # 3 4
Signal at DUT (SPICE simulation)
Delay change
June 8 to 11, 2008
IEEE SW Test Workshop 23

Different loads
Delay change for 3 different cases (10kOhm 2pF, 150 Ohm 2pF, 50 Ohm)
50.0
dT all loads (50%)
40.0
dt [ps]
30.0
20.0
10.0
0.0
1 2
Pos #
3 4
Load has additional impact on skew
June 8 to 11, 2008
IEEE SW Test Workshop 24

Shared resources
Delay change as a result <strong>of</strong> inductance change in
case <strong>of</strong> split lines/ shared drivers
Simplified equivalent circuit
Signal change
June 8 to 11, 2008
IEEE SW Test Workshop 25

Shared resources
Delay change as a result <strong>of</strong> inductance change in
case <strong>of</strong> split lines/ shared drivers
Delay change at 85% level
Delay change at 85% level
(10kOhm/2pF load)
June 8 to 11, 2008
IEEE SW Test Workshop 26

Summary
• Overview to problem <strong>of</strong> ground path provided
• Timing accuracy is sensitive to location <strong>of</strong> ground discontinuity
• Timing accuracy depends on architecture <strong>of</strong> signal delivery system
• Budgeting should be performed
• Compensation seems possible, if trends are known
• Other contributions to timing arise from line length matching, fabrication
variances such as dielectric constant changes, coupled sections,
transitions and other discontinuities on the signal itself and must be
accounted for separately. These contributions have NOT been taken
into account here, yet a significant skew has already accumulated …..
Thank you!
June 8 to 11, 2008
IEEE SW Test Workshop 27