42 service manual.p65 - Super TV Servis M+S

SERVICE MANUAL
Model:
PDP4210EA
Safety Precaution
Technical Specifications
Block Diagram
Circuit Diagram
Basic Operations & Circuit Description
Main IC Specifications
Product Specification of PDP Module
Trouble Shooting Manual of PDP Module
Spare Part List
Exploded View
If you forget your V-Chip Password
Software Upgrade
This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.

Safety Precaution
CAUTION
RISK OF ELECTRIC SHOCK
DO NOT OPEN
CAUTION: TO REDUCE THE RISK OF
ELECTRIC SHOCK, DO NOT REMOVE COVER
(OR BACK). NO USER-SERVICEABLE PARTS
INSIDE. REFER SERVICING TO QUALIFIED
SERVICE PERSONNEL ONLY.
The lightning flash with arrowhead symbol,
within an equilateral triangle, is intended to
alert the user to the presence of uninsulated
“dangerous voltage” within the product’s enclo
sure that may be of sufficient magnitude to
constitute a risk of electric shock to persons.
The exclamation point within an equilateral
triangle is intended to alert the user to the
presence of important operating and
maintenance (servicing) instructions in the
literature accompanying the appliance.
PRECAUTIONS DURING
SERVICING
1. In addition to safety, other parts and
assemblies are specified for conformance with
such regulations as those applying to spurious
radiation. These must also be replaced only
with specified replacements.
Examples: RF converters, tuner units, antenna
selection switches, RF cables, noise-blocking
capacitors, noise-blocking filters, etc.
2. Use specified internal Wiring. Note especially:
1) Wires covered with PVC tubing
2) Double insulated wires
3) High voltage leads
3. Use specified insulating materials for hazardous
live parts. Note especially:
1) Insulating Tape
2) PVC tubing
3) Spacers (insulating barriers)
4) Insulating sheets for transistors
5) Plastic screws for fixing micro switches
4. When replacing AC primary side components
(transformers, power cords, noise blocking
capacitors, etc.), wrap ends of wires securely
about the terminals before soldering.
5. Make sure that wires do not contact heat
generating parts (heat sinks, oxide metal film
resistors, fusible resistors, etc.)
6. Check if replaced wires do not contact sharply
edged or pointed parts.
7. Make sure that foreign objects (screws, solder
droplets, etc.) do not remain inside the set.
MAKE YOUR CONTRIBUTION
TO PROTECT THE
ENVIRONMENT
Used batteries with the ISO symbol
for recycling as well as small accumulators
(rechargeable batteries), mini-batteries (cells) and
starter batteries should not be thrown into the
garbage can.
Please leave them at an appropriate depot.
WARNING:
Before servicing this TV receiver, read the
SAFETY INSTRUCTION and PRODUCT
SAFETY NOTICE.
SAFETY INSTRUCTION
The service should not be attempted by anyone
unfamiliar with the necessary instructions on this
apparatus. The following are the necessary
instructions to be observed before servicing.
1. An isolation transformer should be connected in
the power line between the receiver and the
AC line when a service is performed on the
primary of the converter transformer of the set.
2. Comply with all caution and safety related
provided on the back of the cabinet, inside the
cabinet, on the chassis or picture tube.
3. To avoid a shock hazard, always discharge the
picture tube's anode to the chassis ground
before removing the anode cap.
4. Completely discharge the high potential voltage
of the picture tube before handling. The picture
tube is a vacuum and if broken, the glass will
explode.

5. When replacing a MAIN PCB in the cabinet,
always be certain that all protective are
installed properly such as control knobs,
adjustment covers or shields, barriers, isolation
resistor networks etc.
6. When servicing is required, observe the original
lead dressing. Extra precaution should be given
to assure correct lead dressing in the high
voltage area.
7. Keep wires away from high voltage or high
tempera ture components.
8. Before returning the set to the customer,
always perform an AC leakage current check
on the exposed metallic parts of the cabinet,
such as antennas, terminals, screwheads,metal
overlay, control shafts, etc., to be sure the set
is safe to operate without danger of electrical
shock. Plug the AC line cord directly to the
AC outlet (do not use a line isolation
transformer during this check). Use an AC
voltmeter having 5K ohms volt sensitivity or
more in the following manner.
Connect a 1.5K ohm 10 watt resistor paralleled
by a 0.15µF AC type capacitor, between a
good earth ground (water pipe, conductor etc.,)
and the exposed metallic parts, one at a time.
Measure the AC voltage across the combination
of the 1.5K ohm resistor and 0.15 uF
capacitor. Reverse the AC plug at the AC
outlet and repeat the AC voltage measurements
for each exposed metallic part.
The measured voltage must not exceed 0.3V
RMS.
This corresponds to 0.5mA AC. Any value
exceeding this limit constitutes a potential
shock hazard and must be corrected
immediately.
The resistance measurement should be done
between accessible exposed metal parts and
power cord plug prongs with the power switch
"ON". The resistance should be more than
6M ohms.
AC VOLTMETER
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this
apparatus have special safety-related
characteristics.
These characteristics are offer passed
unnoticed by visual spection and the protection
afforded by them cannot necessarily be obtained
by using replacement components rates for a
higher voltage, wattage, etc.
The replacement parts which have these
special safety characteristics are identified by
marks on the schematic diagram and on the parts
list.
Before replacing any of these components,
read the parts list in this manual carefully. The
use of substitute replacement parts which do not
have the same safety characteristics as specified
in the parts list may create shock, fire, or other
hazards.
9. Must be sure that the ground wire of the AC
inlet is connected with the ground of the
apparatus properly.
Good earth ground
such as the water
pipe, conductor,
etc.
AC Leakage Current Check
Place this probe
on each exposed
metallic part

Technical
Specifications
MODEL :
PDP4210EA
42” Plasma Display
DATE FIRST ISSUED
ISSUE
1
RAISED BY CHECKED BY NUMBER OF PAGES
10
REVISIONS
ISSUED DATE DESCRIPTION RAISED BY :
SPECIFICATION AGREED : SIGNATURE DATE
R & D DEPARTMENT
COMMERCIAL DEPARTMENT
PRODUCTION DEPARTMENT
......................................................................................
......
......................................................................................
......
...........................
...
...........................
...
Q/A DEPARTMENT
......................................................................................
.......
...........................
...
CUSTOMER
......................................................................................
.......
...........................
...
......................................................................................
.......
...........................
...
SPECIFICATION APPROVED :
SIGNATURE : DATE :
.
NOTE :
Only documents stamped “Controlled Document” to be used for manufacture of production parts.

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 2 OF 10 PAGES
1. Standard Test Conditions
All tests shall be performed under the following conditions, unless otherwise specified.
1.1 Ambient light : 150ux (When measuring I B , the ambient luminance
≦0.1Cd/m 2 )
1.2 Viewing distance : 50cm in front of PDP
1.3 Warm up time : 30 minutes
1.4 PDP Panel facing : no restricted
1.5 Measuring Equipment : PC, Chroma 2225 signal generator (with Chroma digital
additional card) or equivalent, Minolta CA100 photometer
1.6 Magnetic field : no restricted
1.7 Control settings : Brightness, Contrast, Tint, Color set at Center(50)
1.8 Power input : 110~120Vac,60Hz
1.9 Ambient temperature : 20°C ± 5°C (68°F ± 9°F)
1.10 Display mode : 31.5KHz/60Hz (Resolution 852 x 480)
1.11 Other conditions :
1.11.1 With image sticking protection of PDP module, the luminance will descend
by time on a same still screen and rapidly go down in 5 minutes. When
measuring the color tracking and luminance of a same still screen, be sure
to accomplish the measurement in one minute to ensure its accuracy.
1.11.2 Due to the structure of PDP, the extra-high-bright same screen should not
hold over 5 minutes for fear of branding on the panel.

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 3 OF 10 PAGES
ELECTRICAL CHARACTERISTICS
2. Power Input
2.1 Voltage : 110 ~120VAC
2.2 Input Current : 3.5A
2.3 Maximum Inrush Current :

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 4 OF 10 PAGES
4.2 Audio input
Audio I/P(L/Rx5) : 1 for DVI
1 for D-Sub
2 for YPbPr
1 for S-Video /AV
4.3 Audio output
Audio O/P(L/Rx1) : Monitor out(L/R)
SPDIF : Optical x 1
5. Environment
5.1 Operating environment
5.1.1 Temperature : 5º to 33°C
5.1.2 Relative humidity: 20% to 85%(non-condensing)
5.2 Storage and Transport
5.2.1 Temperature : -20°C to 60°C(-4º to 140°F)
5.2.2 Relative humidity: 5% to 95%
6. Panel Characteristics
6.1 Type : LG V6
6.2 Size : 42”, 1005mm(width)x597mm(height)x61mm(depth)±1
mm)
6.3 Aspect ratio : 16:9
6.4 Viewing angle : Over 160°
6.5 Resolution : 852x480
6.6 Weight : 14.8kg ±0.5 kg (Net)
6.7 Color : 16.77 million colors by combination of 8 bits R,G,B digital
6.8 Contrast : Average 60:1 (In a bright room with 150Lux at center)
Typical 3000:1 (In a dark room 1/25 White Window
pattern at center).
6.9 Peak brightness : Typical 1000cd/m2 (1/25 White Window)
6.10 Color Coordinate Uniformity : Contrast; Brightness and Color control
at normal setting
Test Pattern : Full white pattern
Average of point A,B,C,D and E +/- 0.01

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 5 OF 10 PAGES
6.11 Color temperature : Contrast at center (50); Brightness center (50);
Color temperature set at Natural
x=0.285±0.02
y=0.293±0.02
6.12 Cell Defect Specifications
Subject to Panel supplier specification as appends.
7. Front Panel Control Button
7.1 CH Up / Down Button : Push the key to changing the channel up or down.
When selecting the item on OSD menu.
Volume Up/ Down Button : Push the key to increase the volume up or down.
When selecting the adjusting item on OSD menu
increase or decrease the data-bar.
Menu Button : Enter to the OSD menu.
Input Select Button : Push the key to select the input signals source.
7.2 Stand by Button : Switch on main power, or switch off to enter power
Saving modes.
7.3 Main Power Switch : Turn on or off the unit.
8. OSD Function
Full on screen display

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 6 OF 10 PAGES
9. Agency Approvals
Safety
Emissions
UL60950
FCC class B
10. Reliability
11.1 MTBF : 20,000 hours(Use moving picture signal at 25°C ambient)
11. Accessories : User manual x1, Remote control x1, Stand x1, Power cord x1,
Battery x 2.

Technical Specifications PDP4210EA
NUMBER 7
OF
10 PAGES
CONTINUATION PAGE
13. Support the Signal Mode
A. VGA and DVI mode
NO.
Resolution
Horizontal
Frequency
(KHz)
Vertical
Frequency
(Hz)
Dot Clock
Frequency
(MHz)
1 640 x 400 31.47 70.08 25.17
2 640 x 480 31.50 60.00 25.18
3 640 x 480 37.50 75.00 31.50
4 640 x 480 37.86 72.81 31.50
5 720 x 400 31.47 70.08 28.32
6 800 x 600 35.16 56.25 36.00
7 800 x 600 37.90 60.32 40.00
8 800 x 600 46.90 75.00 49.50
9 800 x 600 48.08 72.19 50.00
10 832 x 624 49.00 75.00 57.27
11 1024 x 768 48.40 60.00 65.00
12 1024 x 768 56.50 70.00 75.00
13 1024 x 768 60.00 75.00 78.75
14 1152 x 864 63.86 70.02 94.51
15 1152 x 864 67.52 75.02 108.03
16 1280 x 720 45.00 60.00 74.25
17 1280 x 960 60.02 60.02 108.04
18 1280 x 1024 64.00 60.01 108.00
B. HDTV Mode (YPbPr)
NO.
Resolution
Horizontal
Frequency
(KHz)
Vertical
Frequency
(Hz)
Dot Clock
Frequency
(MHz)
1 480i 15.734 59.94 13.50
2 480p(720x480) 31.468 59.94 27.00
3 576p(720x576) 31.25 50.00 27.00
4 720p(1280x720) 37.50 50.00 74.25
5 720p(1280x720) 45.00 60.00 74.25
6 1080i(1920x1080) 33.75 60.00 74.25
- When the signal received by the Display exceeds the allowed range, a warning message
“Main Not Support!” shall appear on the screen.
- You can confirm the input signal format from the on-screen.

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 8 OF 10 PAGES
Remote Control
Standby ( ): Press to turn on and off.
Mute ( ): Press to mute the sound.
Press again to restore the sound.
0~9 Number Buttons: Press 0~9 to
select a channel, and used to input the
password; the channel changes after
2 seconds.
EPG: Press to display EPG mode.
Press it again to exit EPG mode.
Input: Press to select the signal
source, such as TV, AV, S-Video,
Component 1, Component 2, VGA,
DVI or DTV.
DTV: Press to choose DTV directly.
Dot: Press number buttons with it to
select the channels directly in DTV.
VOL +/-: Press to adjust the volume.
CH +/- : Press to select the channel
forward or backward.
MTS: Press repeatedly to cycle through
the Multi-channel TV sound (MTS)
options: Mono, Stereo and SAP
(Second Audio Program).
◄,►,▲,▼, Enter: Press ◄,►,▲,
▼ to move the on-screen cursor. To
select an item, press Enter to confirm.
And it can also press ▲ or ▼ to
select channels, press ◄ or ► to
adjust the volume.
Exit: Press this button to exit.
Menu: Press to enter into the on-screen
setup menu, press again to exit.
V-Chip: Press to select the child
protect mode.
CCD: Press to select the Closed Caption mode.
Freeze: Press to freeze the picture, press again to restore the picture.
Display: Press to display the channel information and it disappear after 3 seconds.
Favorite: Press repeatedly to cycle through the favorite channel list.
Add/Erase: Press to add or delete favorite or dislike channels.
S.Mode: Press repeatedly to cycle through the sound mode: Normal, News, Cinema,
Flat and User.
PIC Size: Press repeatedly to cycle through the picture size that best corresponds your
viewing requirements: Normal, Full, Wide1, Wide2, Wide3, 4:3, No Scale and Panoramic.
(Continued on next page)

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 9 OF 10 PAGES
P.Mode: Press repeatedly to cycle
through the picture mode: Normal,
Vivid, Hi-Bright, User and Dark.
System: Press repeatedly to cycle
through the system options: AUTO,
and NTSC3.58.
Recall: Press to return to previous
channel.
Sleep: Press repeatedly until it
displays the time in minutes (5 Min,
10 Min, 15 Min, 30 Min, 60 Min, 90
Min, 120 Min and, OFF) that you
want the TV to remain on before
shutting off. To cancel sleep time,
press SLEEP repeatedly until sleep
OFF appears.
Red: Press this button to access the
red item or page.
Blue: Press this button to access the
blue item or page.
Green: Press this button to access
the green item or page.
Yellow: Press this button to access
the yellow item or page.
Note: Press CH +/- on the remote control can turn on TV set from standby mode.
Insertion of Batteries:
- Turn the remote control upside down, press and slide off the battery cover.
- Insert two 1.5V (AAA) batteries into the compartment, take care to observe the and
markings indicated inside.
- Replace the cover and slide in reverse until the lock snaps.

Technical Specifications PDP4210EA
CONTINUATION PAGE
NUMBER 10 OF 10 PAGES
PHYSICAL CHARACTERISTICS
14. Power Cord
Length : 1.8m nominal
Type : optional
15. Cabinet
15.1 Color : “Black” colour as defined by colour plaque reference number
15.2 Weight
Net weight : 36.2 kg(with stand) /34.0kg(without stand)
Gross weight : 41.0 kg
15.3 Dimensions(with stand)
Width : 1040 mm
Height : 690 mm
Depth : 290 mm

Block Diagram
Product Specification of PDP Module
LVDS Input
Control Signal
(Serial Interface)
APL Data
Input
Interface
Controller
Memory
Controller
Driver
Timing
Controller
Vs(180V~190V)
Va(55V~65V)
Vcc(+5V)
Display data, Driver timing
Scan Driver
Color Plasma Display Panel
852 X 480 pixels
Address Driver
Common sustain driver
Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.

Block Diagram
X6965D
SAW Filter
(U9)
Coaxial
TD1336
Tuner(U8)
UPC3218
AGC Amplifier
(U10)
2nd_IF+ & 2nd_IF-
Differential Data Stream
MT5111
DTV Front-end
(U11)
74HC74
(U12)
TS[0...7]
EEPROM
24C16(U13)
I2C
256Mb DDR
(U15)
MT5351
DTV Back-end
(U14)
I2C
32Mb
Flash(U17)
256Mb DDR
(U18)
SPD
Video Data[0...23]
Audio Data
Control
Signals
Connect with
MT8205

Block Diagram
Power Connector
(Supplied by PDP)
To PDP
5V
3.3V
2.5V
1.25V
1.8V
To PDP
From MT 5351
3.3V
DVI
SiI161B
(SiI169)
DVI Reciver
(U18)
5V
DVII2C
YpbPr×2
Vedio[0...23]
Video[0...23]
BA7612F
(U23)
VGA
Audio
Control Signals
EEPROM
24C02(U19)
IDTQS3
VH257
(U16)
74LVC244A
U30-U33
I2C (MT8205 I2C)
CVBS×2 (CVBS0 is from tuner.)
V_BYPASS
S-Video
TV
AV
YPbPr
PDP Connector
LVDS Data
PDP Control Signals
RGB Output
MT8205
(U7)
3.3V
2.5V
1.8V
Data[0...31]
Address[0...11]
Flash
16M-BIT(U9)
DDR
128Mb(U10)
DDR
128Mb(U11)
3.3V
2.5V
1.25V
LP2996
(U12)
1.25V
2.5V
From MT3551
RS232
Signals
3.3V
5V
VGAI2C
MX232A
(U1)
EEPOROM
24C02(U14)
TTL Signals
(Used by MT8205)
UART0 (Communication with MT5351)
UART2 (MT5351 DownLoad)
AV1 Audio
AV2 Audio
DVI Audio in
YPbPr Audio in
CD4052
(U17)
IDTQS3VH257
(U25)
AV Audio in
Din
Dout
MT8776
(U20)
Audio L
& Audio R
5V
Bypass Out
CS4334
(U22)
Audio Bypass
5V
I2C
MT8205 I2C
I2C
EEPROM
24C16(U2)
5V

Circuit Diagram
- Power supply board of PDP Module, DGP-420WXGA
- Power supply board of PDP Module, USP490M-42LP
- Main (Video) board
- Audio/Tuner board
- ATSC board
- Keypad board
- Remote control receiver board
- External L/R Speakers board
- Remote control board

2
5
1
6
4
3
4
9
2
5
1
4
3
3
3
3
4
4
2
1
2
3
4
5
6
7
8
9
6
4
6
4
2
4
3
2
1
D
1
2
CN02
3-176976-1
F101
250VAC 8A
PFC+
VI
R102
1W 390KJ
1
2
CN03
3-176976-1
TNR101
14D 621K
R117
180KF
CN01
3-176976-2
R118
180KF
L101
23mH
C101
275VAC 1uF
L102
23mH
R119
180KF
L103
CH108200S
R120
160KF
R121
160KF
R122
18KF
L104
CH108200S
C102,103
250V 0.001uF
R129
150KF
RYC
C112
330pF
R108
5W 15
RELAY1
SDT-SH-118DM
D103
LL4148
R123
330KF
R103
5W 20
C113
2.2uF
TNR102
14D 621K
C111
0.1uF
C110
470pF
R124
220KF
7
6
VO
IA
VI
BD101
D25XB60
R116
10KF
11
VS
RE
R115
1.5KF
PK
R114 3K
MO
IS
U101 UC3854N
C104
630V 1uF
R104
10W 0.02
R112
C108
680pF
CA
GT
16
3KF
T208
PFC COIL 200uH
R113
24KF
D109
1N5236B
C109
68PF
R111
100F
Q102,Q103,Q109
SPW20N60C3*3
R109
1W 4.7
Q104
KTC3209
Q105
KTA1281
R106
1W 4.7
D102
FEP30JP
R107
1W 4.7
R110
10KF
C123
35V 47uF
C105,106
450V 330uF
R176
10KF
PC102
PC-17K1C
R144
10F
Q106
KSP2907
PFC+
PFC VCC
PFC +
VA VCC
D204
LL4148
R221
2.2M
R222
2.2M
R223
2.2M
R224
2.2M
R225
1M
R226
2W 240K
D205
BYV26EGP
C206
630V 0.047uF
D213
LL4148
C220
R227
1W 4.7
35V 47uF
Q206
KTA1281
Q203,204
SPW11N80C3*2
R228
1W 4.7
R230
4.7KF
T204,205
VS EER4042
R232
1K
D600
FSF10A60
R600
1W4R7
D601
FSF10A60
R603
1W4R7
R231
5W 0.05
C600
1KV 220pF
C601
1KV 220pF
R620
2W 100K
C222
630V 0.1uF
C221
630V 0.1uF
R602
2W 100K
C602
250V 820uF
R604
120KF
R606
270KF
R609
300KF
R610
300KF
R611
300KF
R612
12KF
R613
120KF
R627
120KF
190VS
VS DET
GND
190VS
D
R125
75KF
R126
75KF
R127
75KF
R128
75KF
R130
240KF
R132
33KF
R133
33KF
C114
0.68uF
R131
33KF
R134
24KF
8
VR
SS
CT
T100
STBY EE1927
RS
13
C115 50V 10uF
14
C116 0.0022uF
12
R135 10KF
GND
VC
15
EN
10
C117
35V 470uF
R136
10KF
R137
10KF
L301
D111
1N4148
RYC
R233
100KF
Q207
KRC103M
C209
C210
R235
C211
R236
R260
2.4KF
1uF
0.001uF
4.7KF
0.001uF
10KF
8
7
1
2
PC204
PC-17K1C
CS
CT
RT
FB
VCC
GND
OUT
IS +
5
3
IC201
KA7552A
R243
1W 47R
C212
0.0047uF
PC204
Q702
KTC3207
R628
120KF
R607
130KF
R608
120KF
VR601
5K
C
D107
US1M
R199
56KF
R198
56KF
PFC+
AC-1
R196
56KF
R195
56KF
R193
56KF
R192
56KF
R189
200KF
R190
200KF
C126
250V 0.47uF
R140
7.5KF
R141
4.7KF
Q107
KTC3198Y
C118
0.01uF
PC100
R142
6.8KF
R175
0
1
GND DRAIN
2
R143
3W 470K
D108 1N5236B
VCC
FB
C119 0.1uF
R145
2W 240K
PC101
PC-17K1C
D104
US1M
U100
5M0280R-YDTU
C121
630V 0.01uF
D105
US1M
C120
35V 47uF
D300
SB560
R146
2W 100
D301
US1M
R305
5W15
VA
C301,301A
10V 2200uF*2
R155
100KF
R151
100KF
27uH
R152
100KF
R150
100KF
R154
100KF
R149
100KF
R301
220F
PC101
IC300
KA431AZ
R153
100KF
R148
100KF
C302
0.68uF
D302
US1M
R306
5W6.8
R307
5W6.8
R302
1.02KF
R303
1KF
VS
AC DET
PC100
PC-17K1C
PC102
+5VSTBY
GND
PFC ON/OFF
PFC +
VA VCC
D226
LL4148
R253
2W 240K
C263
10uF
C213
630V 0.01uF
D209
LL4148
C225
0.1uF
D208
BYV26EGP
Q209
SPW11N80C3
R229
1W 4.7F
T206
VA EER4042
R700
1W 10
D700
FSF10A60
C700
1KV 100pF
C701,702,704
100V 330uF
D211
1N5234B
R704
22KF
R705
20KF
R706
20KF
R707
2.7KF
R615
18KF
60VA
VA DET
C
PFC VCC
R156
1KF
Q300
FQP17N40
Q208
KTA1281
R245
10KF
GND
PFC GND
C128
35V 470uF
D106
US1M
방전 CTL
Q108
KTC3198Y
D303
1N5245B
C304
50V 4.7uF
R247
1.2K
R246
5W 0.2
R715
45.3KF
R716
45.3KF
R720
45.3KF
R710
18KF
R701
18KF
R708
18KF
R702
33KF
60VA
B
PFC +
MULTI VCC
R216
100KF
PC201 PC-17K1C
Q202
KRC103M
R217
10KF
C201
0.01uF
D200
LL4148
C203
C204
R218
C205
R219
10K
R262
1KF
C262
4.7uF
T207
MULTI EER4042
R209
2W 240K
D202
BYV26EGP
C200
630V 0.01uF
Q201
SPW11N80C3
D206
LL4148 R210
D203
1W 10F
LL4148
R212
Q200 10KF
KTA1281
R214 R237
360RF 5W 0.1
C202 35V 47uF
1uF
8
CS
0.001uF 7
CT
4.7KF 1
RT
0.22uF 2
FB
GND
VCC
OUT
5
R220
1/4W 100R
IS +
3
IC200
KA7552A
C208
470pF
PC202
PC-17K1C
C227
0.001uF
R500 C500
1W 10 1KV0.001uF
L500
C550~C554
6*20 2.5uH
10V 2200uF*5
D500
SF30SC6
R520
470F
D5001
PC202
SF30SC6
C530
1uF
IC500A
KA431AZ
IC500
R505 C505
KA317
1W 4R7 1KV 0.001uF
D501
SUF30J
C506
R507
50V 220uF 5W 2.7K
IC501
KIA278R12PI
C519 R531
D502
31GF6
D503
D10L20U
C516
35V 1000uF
1
Adj Output
2
1
Vin
Vo
2
R532
C510
1W 2.7K
35V 470uF
IC502
KIA378R09PI
C520 R526
Input
GND
ON/OFF
1
Vin
Vo
2
GND
ON/OFF
VR500
2K
PC201
R501
3.3KF
R522
4.7KF
R525
56KF
R509
3.3KF
R508
0R
C504,C555~C557
10V 2200uF*4
C507
35V 47uF
C511
35V 47uF
C514
35V 47uF
R510
5W 1K
R513
2.7KF
R514
2KF
R515
1.8KF
R518
3.9KF
J2
0
R502
0
R503
1KF
R504
1.8KF
R511
15KF
R512
15KF
R516
1KF
R519
1.5KF
MULTI ON/OFF
+5VCTRL
5VSC
+5V DET
GND
+30V/1.0A (+24V/1.25A)
+30V DET
5VCTRL
SEL
CABLE
GND
+12V /1.0A
+12V DET
GND
9VSC
+9V DET
PC205
PC-17K1C
C215 35V 47uF
R248
C216 1uF
8
100KF
CS
5
C217 0.001uF
OUT
7
CT
R252
R250 4.7KF
1
1W 100R
RT
3
Q210
C218 0.047uF
IS +
2
KRC103M
FB
R251 10KF
IC202
KA7552A
R261
1KF
R249
PC206
10KF C214
PC-17K1C
0.01uF
C226
C261 0.001uF
4.7uF
R400
LED401
1KF
RED
R401 1KF
R402 4.7KF
IC400
KIA7045AP
1
VCC OUT
3
LED400
CRST400
GREEN
4MHZ
C400
C401
50V 0.1uF
50V 0.1uF
1
Xin Xout
3
GND
RA3/AN3
24
RA2/AN2
23
RA1/AN1
22
RA0/EC0
21
RC1
20
RC0
19
Vss
18
|RESET
17
Xout
16
Xin
15
RD3
14
IC401
HMS87C1304A
GND
VCC
AN4/RA4
AN5/RA5
AN6/RA6
AN6/RA6
VDD
RD0
RD1
AN0/AVref/RB0
BUZ/RB1
INT0/RB2
INT1/RB3
10
11
GND
12
PWM0/COMP0/RB4 RD2
13
R415 100F
R416 1KF
C219
0.01uF
R421 10KF
R718
45.3KF
C410 50V0.01uF
R422 10KF
C411 50V0.01uF
R717
45.3KF
R721
45.3KF
NO
1
R712
18KF
PC206
Q701
KTC3207
D212
1N5234B
R714
18KF
일자/사유
R719
18KF
REVISION HISTORY
변경
전
R703
36KF
R709
36KF
VR700
5K
R711
11KF
PC205
2004/07/28 PH967C6
FEP30JP
변경
후
DGP-420WXGA
VA ON/OFF
B
A
ACD
RLY_ON
SB5V
VS_ON
5VD
CN801
1
2
3
4 24V/30V
5
6
7
171825-7
5VSC
12VSC
CN802
1
2
3
4
171825-4
CN803
1
2
3
4
5
6
7
8
9
10
11
12
1-171825-2
9VSC
5VSC
CN804
1
2
3
4
5
6 5VCTRL
7
8
9
171825-9
60VA
CN805
4
3
2 190VS
1
1-1123723-4
CN806
10
9
8
7
6
5
4
3
2
1
1-1123723-0
190VS
60VA
5VCTRL
CN807
1 5VCTRL
2
3
4
5
6
7
8
1-1123723-8
CN808
1
2
3
4
5
6
7 9VSC
8
171825-8
GND
CN809
1
2
171825-2
C403 50V 0.68uF
C404 50V 0.1uF
C405 50V 0.1uF
C406 50V 0.1uF
C407 50V 0.1uF
C408 50V 0.1uF
C409 50V 0.1uF
R403 1KF
R404 1KF
R405 1KF
R406 1KF
R407 1KF
R408 1KF
R409 2KF
R410 330F R411 330F
R423 1KF
R412 1KF
R414 2KF
R417 1KF
R418 1KF
R420 4.7KF
9
7 17 16 4
6
20
19 3
11 12
13 2 15
5
21 8
18 1
+5VSTBY
GND
GND
VS DET
VA DET
+5V DET
+12V DET
+9V DET
+30V DET
PFC ON/OFF
VA,VS ON/OFF
방전CTL
AC DET
MULTI ON/OFF
ACD OUT
5VD OUT
VS ON
RLY ON
RY ON/OFF
HIC_MICOM
SW400
JSS 2209
m
<

USP490M-42LP

A
1
1
1
1
1
1
1
1
+
1
B
C
D
E
MT8205E (PBGA388) LCDTV BOARD 4 LAYERS
1. INDEX
DV18A
RSRXD
RSRXD 6
RSTXD
4 RSTXD 6
4
PCRXD
Power down Reset circuit
PCRXD 13
2. LDO
PCTXD
PCTXD 13
R73 10/NC
TXD
TXD 3,13
CE88
2N3904
RXD
RXD 3,13
3. MT8205E PBGA388
DV33A R341 10
3 2 R342 URST#
SCL
SCL 7,10
0
SDA
SDA 7,10
47uF/16v
Q14
URST#
URST# 3
4. MT8205 ANALOG DECOUPLING
CB136
D28
0.1uF
+12V
+12V 7,10,13,14
1N4148
TUNER_12V
TUNER_12V 7
5. DDR MEMORY & FLASH
8205UP3_1
8205UP3_1 3
PWR_GND
PWR_GND 11
INVERTER_PWR
INVERTER_PWR 11
6. VGA IN & PC AUDIO IN
GPIO_DVD1
GPIO_DVD1 3
DV18A
DV18A 2,3
ADD BY MTK
7. VIDEO IN & TUNER IO
8. AUDIO/VIDEO IN CIRCUIT
9. DVI INPUT
10.LVDS/CRT/TTL OUT
11.BACK LIGHT / KEYPAD
12.WM8776 & A/V BYPASS
RSTXD
PCTXD
5VSB
U1
INVERTER_PWR
13.ATSC INTERFACE
13
5VSB DV33A
J3
R1IN
R1OUT
12
8
R2IN
R2OUT
9
11
INVERTER_PWR
T1IN
T1OUT
14
1
3
14.PDP INTERFACE
+ CE1
10
R335
2
3
T2IN
T2OUT
7
R336
220uF/16v
0/NC 0
3
C220UF16V/D6H11
C1 0.1uF 1
4
5VSB
C+
3
ADD BY MTK
5
C2 0.1uF
C1-
4
C2+
VCC 16
6
5
7
C3 0.1uF
C2-
2
C4
PWR_GND
V+
8
6
0.1uF
C5 0.1uF
V-
GND 15 8x1 W/HOUSING
MAX232A
DIP8/W/H/P2.54
RSRXD
PCRXD
H1
HOLE/GND
9
8
7
6
9
8
7
6
2
3
4
5
2
3
4
5
5VSB
SYSTEM EEPROM
5VSB
R1
10k
R112
J1
R337 R3 R4
R 8205UP3_1 LOW :POWER ON
10k 10K 10K
R0603/SMD
R5 R6
CB1
U2
5 SYS_PWR
10k 10k
J4
1
NC VCC 8 4
5VSB
Q1
HOLE/GND
0.1uF 2
GPIO_DVD1
H2
NC WP
7
3
1
3
SCL
R2
RxD
NC SCL
6
2
2
9
4
SDA
8205UP3_1
TxD
9
2
2
GND SDA 5
1
1
3
8
8
3
3
Add by MTK
4
7
4.7k
7
4
4
SOT23/SMD
EEPROM 24C16
5x1 W/HOUSING
6
6
5
5
2N3904
SOP8/SMD
PH5/2.0
RS-232
4x1 W/HOUSING
C132 C133
DIP4/W/H/P2.0
2 2
20pF 20pF
5VSB
3 2
8205UP3_1 HIGH :POWER OFF
DV33A
Add by MTK
VCC
9
8
7
6
H3
9
8
7
6
HOLE/GND
2
2
3
3
4
4
5
5
PWR_GND
L44
FB
BEAD/SMD/1206
L50
FB
BEAD/SMD/1206
J2
1
2
3
4
5
6
7
8
9
10
11
+12V
+12V
+ CE2
220uF/16v
C220UF16V/D6H11
L1
FB
BEAD/SMD/0805
For Tuner
+ CE3
47uF/16v
TUNER_12V
CB2
0.1uF
AUIO IN/OUT GND
ANALOG INPUT GND
DIGITAL GND
DIP11/P2.54
H4
HOLE/GND
9
9
2
2
8
8
3
3
7
7
4
4
From Power board.
6
6
5
5
VCC
J21
1
2
3
4
1 5
1
6
+12V
7
8
9
1 M1 1 M2 1 M3
10
1
V1
1
V2 1
V3 1
V4
CON10
Title
Size Doc Number R e v
C
INDEX V1.2
Wednesday, October 12, 2005
Date: Sheet o f
1 15
A
B
C
D
E

A
1
1
1
1
B
C
D
E
4 4
R96 0/NC
Power ON alive source
R0805/SMD
VCC
DV33
5VSB
TP1
U3 CM1117-3.3V
U4 CM1117-3.3V
TEST POINT DIP1.0
L2
L3
Vout
3
DV33
IN OUT
2
3
IN OUT
2
FB
CE4
FB
BEAD/SMD/0805
+
BEAD/SMD/0805
+ CE5
+ CE6
CB3
+ CE7
220uF/16v
CB4
220uF/16v
CB5
220uF/16v
0.1uF
220uF/16v CB6
3 0.1uF
SOT223/SMD
0.1uF
SOT223/SMD
0.1uF
3
ADJ/GND
ADJ/GND
R99 0/NC
R0805/SMD
AV33
DV33A
3
IN
U5 CM1117-3.3V
ADJ/GND
OUT
2
SOT223/SMD
L4
FB
BEAD/SMD/0805
+ CE8
220uF/16v
C6
10uF/10v
AV33
CB7
0.1uF
+ CE9
100uF/16v
CB8
0.1uF
3
IN
U6 CM1117-1.8V
ADJ/GND
OUT
2
SOT223/SMD
+ CE10
220uF/16v
CB9
0.1uF
L5
FB
BEAD/SMD/0805
DV33A
DV18A
TP2
DV18A
DV18A
DV18A 1,3
2 2
1 1
Title
Size Doc Number R e v
C
LDO V1.2
Wednesday, October 12, 2005
Date: Sheet o f
2 15
A
B
C
D
E

C
D
DV33A
R106 0
5VSB
U27
R104
LM809
SOT23/SMD
DVIODCK
DVIODCK 9,13
RSTVCC URST#
DVIDE
IN OUT
DVIDE 9,13
DVIHSYNC
DVIHSYNC 9,13
DVIVSYNC
DVIVSYNC 9,13
CB135 + CE81
R270
A_DQS[0..3] A_DQS[0..3] 5
0.1uF 22uF/25v
100K
A_RA[0..11] A_RA[0..11] 5
A_BA[0..1] A_BA[0..1] 5
A_DQM[0..1] A_DQM[0..1] 5
A_DQ[0..31] A_DQ[0..31] 5
A_CLK
A_CLK 5
XTALI
A_CLK#
A_CLK# 5
XTALI 4
XTALO
U7
A_CKE
A_CKE 5
4 XTALO 4
4
ANALOGVDD
A_CS#
A_CS# 5
ANALOGVDD 4
External Reset Circuit
ADCVDD
A_RAS# A_RAS# 5
ADCVDD 4
APLLVDD
A_CAS# A_CAS# 5
APLLVDD 4
VPLLVDD
ADCVDD4
DVIDE
A_WE#
A_WE# 5
VPLLVDD 4
C3
ADCPLLVDD1
ADCVDD4
VFEVDD1
DE_DVI
C24
DVIVSYNC
SDV25
SDV25 5
ADCPLLVDD1 4
D3
ADCPLLVDD
MPX1
ADCVDD4
VSYNC_DVI
D24
DVIHSYNC
VREF
ADCPLLVDD 4
C1
VREF 5
AUXTOP
MPX2
SIF
HSYNC_DVI
A24
DV18A
ORO7
AUXTOP 4
C2
AUXBOTTOM
GND
AF
DVDD18
Y24
ORO7 12
ORO4
AUXBOTTOM 4
L11
REXTA
VREFP4
ADCVSS4
AOSDATA0
A25
ORO4 12
AOSDATA1
ORO2
REXTA 4
D1
APLL_CAP
VREFN4
REFP4
AOSDATA1
A26
VI[0..23]
ORO2 7
DV33A
APLL_CAP 4
D2
VI[0..23] 9,13
PWM2VREF
GND
REFN4
AOSDATA2
B26
DV33A
F_A[0..20] F_A[0..20] 5
PWM2VREF 4
F2
ADCVDD0
ADIN4
ADCVSS
DVDD3I
F23
AOSDATA3
F_D[0..7] F_D[0..7] 5
ADCVDD0 4
D4
ADCVDD4
ADIN3
ADIN4
AOSDATA3
B25
DOUT
DV33A
F_OE#
F_OE# 5
ADCVDD4 4
E1
AVCM
ADIN2
ADIN3
LIN B24
DACBCLK
AVCM 4
E2
VOCM
ADIN1
ADIN2
AOBCK C26
DACLRC
VOCM 4
E3
VICM
ADIN0
ADIN1
AOLRCK C25
DACMCLK
TXD
VICM 4
E4
R7
VREFP4
ADCVDD
ADIN0
AOMCLK E24
D1
TXD 1,13
GND
RXD
VREFP4 4
F1
10K/NC
VREFN4
PWM2VREF
ADCVDD
DVSS3
N15
RXD 1,13
A_DQ24
WE#
VREFN4 4
F4
DACFS
AUXTOP
PWM2VREF
DQ24
G26
WE# 13
A_DQ25
PCE#
DACFS 4
F3
DACVREF
AUXBOTTOM
AUXVTOP
DQ25
G25
1N4148/SMD
PCE# 5
A_DQ26
8205UP3_0
DACVREF 4
G3
DACVDD
GND
AUXVBOTTOM
DQ26
F26
8205UP3_0 11
SDV25
URST#
MPX1
DACVDD 4
J3
LVDDA
VPLLVDD
VPLLVSS
DVDD2
F24
MPX1 8
A_DQ27
MPX2
LVDDA 4
G4
IR
VPLLVDD
VPLLVDD
DQ27
F25
MPX2 8
A_DQ28
IR 7,11
H3
GND
DLLVDD
DQ28
E26
K3
GND
VSYNC
VSYNC 10
GND
DLLVSS
DVSS2
N16
K4
A_DQ29
+ CE11
HSYNC HSYNC 10
REXTA
BGVSS
DQ29
E25
J4
SDV25
VPLLVDD
REXTA
DVDD2
G24
H4
A_DQ30
10uF/25v/NC
LVDDA
BGVDD
DQ30
D26
L3
A_DQ31
OGO[0..6] OGO[0..6] 7,9,13
AP7
LVDDA
DQ31
D25
G2
A_DQS3
A7P
DQS3
H25
G1
A_DQM1
OBO[0..7] OBO[0..7] 11
A7N
DQM1
H26
H2
GND
AP[0..7] AP[0..7] 10
CLK2P
DVSS18
P14
H1
A_DQS2
AN[0..6] AN[0..6] 10
GND
CLK2N
DQS2
J25
M12
A_DQ23
R
AP6
LVSSA
DQ23
J26
Internal Reset Circuit
R 10
J2
A_DQ22
G
AN6
A6P
DQ22
K25
G 10
J1
GND
B
AP5
A6N
DVSS2
P16
B 10
K2
A_DQ21
AN5
A5P
DQ21
K26
K1
A_DQ20
RED+
RED+ 8
3 LVDDA
A5N
DQ20
L25
L4
DV18A
RED-
RED- 8
3
AP4
LVDDB
DVDD18
AA24
L2
A_DQ19
DV33A
GREEN+ GREEN+ 8
AN4
A4P
DQ19
L26
L1
SDV25
GREEN- GREEN- 8
AP3
A4N
DVDD2
H24
M2
A_DQ18
BLUE+
BLUE+ 8
AN3
A3P
DQ18
M25
M1
A_DQ17
BLUE-
BLUE- 8
GND
A3N
DQ17
M26
M11
A_DQ16
R8
CVBS1+ CVBS1+ 8
CLK1+
LVSSB
DQ16
N25
N2
A_RA4
47k
CVBS1-
CVBS1- 8
CLK1-
CLK1P
RA4
J23
N1
GND
CVBS2+ CVBS2+ 8
AP2
CLK1N
DVSS2
R16
P2
A_RA5
CVBS2-
CVBS2- 8
AN2
A2P
RA5
J24
P1
A_RA6
CVBS0+ CVBS0+ 8
LVDDA
A2N
MT8205
RA6
K23
M3
A_RA7
DACBCLK
CVBS0-
CVBS0- 8
AP1
LVDDC
RA7
K24
R2
A_RA8
SOY
SOY 7
AN1
A1P
RA8
L23
R1
GND
GND
SY+
SY+ 8
AP0
A1N
DVSS18
R14
T2
A_RA9
SY-
SY- 8
AN0
A0P
RA9
L24
T1
A_RA11
SC+
SC+ 8
GND
A0N
RA11
M23
N12
A_CKE
SC-
SC- 8
DACVDD
LVSSC
CKE N26
N3
SDV25
Y+
Y+ 8
DACVREF
DACVDDC
DVDD2
H23
M4
A_CLK
Y-
Y- 8
DACFS
VREF
RCLK P26
N4
A_CLK#
CB+
CB+ 8
GND
FS
RCLKB P25
N11
GND
CB-
CB- 8
DACVSSC
DVSS2
P15
T4
A_RA3
CR+
CR+ 8
DACVDD
SVM
RA3
M24
P3
A_RA2
CR-
CR- 8
GND
DACVDDB
RA2
N23
R3
A_RA1
CLK1+
CLK1+ 10
DACVDD
DACVSSB
RA1
N24
P4
A_RA0
CLK1-
CLK1- 10
G
DACVDDA
RA0
R26
U4
A_RA10
GND
G
RA10
P24
R4
A_BA1
B
DACVSSA
BA1
P23
U3
SDV25
SCL_8205 SCL_8205 10
R
B
DVDD2I
U23
V4
DV18A
SDA_8205 SDA_8205 10
R
DVDD18
AA23
T3
A_BA0
VSYNC
DE
BA0
R24
U1
A_CS#
HSYNC
VSYNCO
RCS#
R23
U2
A_RAS#
HSYNCO
RAS#
T24
V1
GND
DACBCLK DACBCLK 12
VCLK
DVSS2
R15
V2
A_CAS#
DACMCLK DACMCLK 12
EBO7
CAS#
T23
V3
A_WE#
DACLRC DACLRC 12
EBO6
RWE#
U24
W1
A_DQ8
DOUT
DOUT 12
EBO5
DQ8
W26
W2
A_DQ9
AOSDATA1 AOSDATA1 12
DV33A
EBO4
DQ9
V25
AC9
A_DQ10
AOSDATA3 AOSDATA3 12
DVDD3I
DQ10
V26
W3
SDV25
MUTE
MUTE 12
2 EBO3
DVDD2
V23
2
W4
A_DQ11
EBO2
DQ11
U25
Y1
GND
EBO1
DVSS18
T13
Y2
A_DQ12
VGASOG VGASOG 8
EBO0
DQ12
U26
Y3
A_DQ13
HSYNC_VGA HSYNC_VGA 6
GND
EGO7
DQ13
T25
P11
GND
VGAVSYNC#
DVSS18
DVSS2
T15
VGAVSYNC# 6
Y4
A_DQ14
EGO6
DQ14
T26
AA1
A_DQ15
PWM0
EGO5
DQ15
R25
PWM0 11
AA2
A_DQS1
8205UP3_1
EGO4
DQS1
W25
8205UP3_1 1
AA3
GND
8205UP1_2
EGO3
AVSS18
W23
8205UP1_2 9,11
AA4
DV18A
8205UP1_3
EGO2
AVDD18
Y23
8205UP1_3 13
AB1
VREF
SW
EGO1
RVREF
G23
SW 13
AB2
GND
OGO7
EGO0
DVSS18
T16
OGO7 12
AB3
A_DQM0
PWM1
ERO7
DQM0
Y26
PWM1 12
AB4
A_DQS0
OGO4
ERO6
DQS0
Y25
OGO4 9,13
AC1
A_DQ7
DVISCL
DVISCL 9
DV18A
ERO5
DQ7
AA26
AC18
SDV25
DVISDA
DVDD18
DVDD2
V24
DVISDA 9
AC2
A_DQ6
ERO4
DQ6
AA25
AC3
A_DQ5
ERO3
DQ5
AB26
AC4
GND
GND
ERO2
DVSS2
T14
R11
A_DQ4
GPIO_DVD0
DVSS3
DQ4
AB25
GPIO_DVD0 7
AD1
A_DQ3
GPIO_DVD1
ERO1
DQ3
AC26
GPIO_DVD1 1
AD2
SDV25
GPIO_DVD2 GPIO_DVD2 7
OBO7
ERO0
DVDD2
W24
AD3
A_DQ2
DVD GPIO PORTS
OBO6
OBO7
DQ2
AC25
AD4
A_DQ1
OBO5
OBO6
DQ1
AD26
AE1
A_DQ0
OBO5
DQ0
AD25
PDP power cotrol GPIO.
ORO1
ORO1 10,14
BGA388/SOCKET
ORO3
ORO3 10,14
MT8205
ORO5
ORO5 10
8205UP1_4
8205UP1_4 10
REQUEST#
REQUEST# 13
1 HWSDA R15 R/NC SDA_8205
READY#
1
READY# 13
HWSCL R16 R/NC SCL_8205
C
D
A
A
B
B
E
E
OBO4 AE2
OBO3 AF1
OBO2 AF2
OBO1 AE3
OBO0 AF3
OGO7 AE4
OGO6 AF4
OGO5 AC5
GND T11
OGO4 AD5
OGO3 AE5
OGO2 AF5
OGO1 AC6
DV33A AD9
OGO0 AD6
ORO7 AE6
ORO6 AF6
ORO5 AC7
ORO4 AD7
DV18A AD18
ORO3 AE7
ORO2 AF7
ORO1 AC8
MUTE AD8
F_A15 AF8
GND P12
F_A14 AE9
F_A13 AF9
F_A12 AE10
F_A11 AF10
F_A10 AC11
F_A9 AD11
F_A8 AF12
F_D0 AE15
F_D1 AD15
DV18A AC19
F_D2 AC15
F_D3 AF16
F_D4 AE16
GND R12
F_D5 AD16
F_D6 AC16
F_D7 AF17
F_A0 AD17
F_A1 AD14
F_A2 AE14
F_A3 AF14
F_A4 AF13
F_A5 AE13
F_A6 AD13
F_A7 AC13
F_A16 AE8
DV33A AC10
F_A17 AC17
F_A18 AE12
F_A19 AD12
F_A20 AE11
GND T12
F_A21 AF11
AE17
F_OE# AF15
WE# AC12
PCE# AC14
AF18
AE18
DV33A AD10
AF19
8205UP1_2AE19
8205UP1_3AF20
8205UP1_4AE20
DV18A AD19
GPIO_DVD1 AD20
AC20
AF21
8205UP3_0AE21
8205UP3_1AD21
GND P13
URST# AC21
UP3_4 AD22
UP3_5 AC22
GPIO_DVD2 AF22
GPIO_DVD0 AE22
SW AF23
GPIO AE23
PWM0 AD23
PWM1 AC23
IR AF24
RxD AE24
TxD AD24
GND R13
ICE AC24
HWSCL AF25
HWSDA AE25
DVISCL AF26
DVISDA AE26
REQUEST# AB23
READY# AB24
ADCVDD0
RED-
RED+
GREEN-
GREEN+
VGASOG
BLUE-
BLUE+
GND
GND
AVCM
ADCVDD0
CVBS2-
CVBS2+
CVBS1-
CVBS1+
CVBS0-
CVBS0+
GND
SY+
GND
ADCVDD0
SC-
SC+
SY-
ADCVDD0
VOCM
GND
VICM
ADCVDD0
CR-
CR+
CB-
CB+
Y-
Y+
SOY
GND
VGAVSYNC#
HSYNC_VGA
GND
DV18A
GND
ADCPLLVDD1
ADCPLLVDD
GND
GND
ANALOGVDD
ANALOGVDD
XTALO
XTALI
GND
APLL_CAP
GND
APLLVDD
ANALOGVDD
GND
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DV18A
VI7
VI8
VI9
VI10
VI11
GND
VI13
VI12
VI14
VI15
GND
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
DVIODCK
UP3_4 FOR S/W SCL
UP3_5 FOR S/W SDA
PDP signal cotrol GPIO.
GPIO
GPIO 7,10
ORO6
ORO6 10
UP3_5 R17 0
F_A21
F_A21 9
UP3_4 R18 0
ADIN4
ADIN4 14
R9
URST#
URST# 1
Change by MTK
1k
DV18A
DV18A 1,2
ADIN3 R365 10K
ADIN2 R366 10K
ADIN1 R367 10K
DV33A DV18A
ADIN0 R368 10K
DV33A
DV18A
Title
Size Doc Number R e v
C
MT5205BGA388 V1.2
Date: Wednesday, October 12, 2005
Sheet 3 o f 15
0
3
2
OBO4
OBO3
OBO2
OBO1
OBO0
OGO7
OGO6
OGO5
DVSS18
OGO4
OGO3
OGO2
OGO1
DVDD3
OGO0
ORO7
ORO6
ORO5
ORO4
DVDD18
ORO3
ORO2
ORO1
ORO0
HIGHA7
DVSS18
HIGHA6
HIGHA5
HIGHA4
HIGHA3
HIGHA2
HIGHA1
HIGHA0
AD0
AD1
DVDD18
AD2
AD3
AD4
DVSS3
AD5
AD6
AD7
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
A16
DVDD3I
A17
IOA18
IOA19
IOA20
DVSS18
IOA21
IOALE
IOOE#
IOWR#
IOCS#
WR#
RD#
DVDD3
INT0#
UP12
UP13
UP14
DVDD18
UP15
UP16
UP17
UP30
UP31
DVSS18
PRST#
UP34
UP35
FCICLK
FCICMD
FCIDAT
GPIO0
PWM0
PWM1
IR
RXD
TXD
DVSS3
ICE
SCL
SDA
SCL0
SDA0
SCL1
SDA1
VFEVSS1
L12
AVCM D5
C4
ADCVDD0
CVBS2N B1
CVBS2P A1
CVBS1N B2
CVBS1P A2
CVBS0N B3
CVBS0P A3
ADCVSS0
REFP0
REFN0
ADCVDD1
SCN B5
SCP A5
SYN B6
SYP A6
ADCVSS1
M13
REFP1
D6
REFN1
C6
VFEVDD0
D7
VOCM B7
VFEVSS0
N13
VICM A7
ADCVDD2
C7
CRN B8
CRP A8
CBN B9
CBP A9
YN B10
ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3
ADCVSS3
REFP3
REFN3
VSYNC C13
HSYNC C14
DVSS N14
DVDD D14
L14
D15
ADCPLLVSS1
L13
B4
A4
C5
YP A10
SOY C8
D10
D9
C9
D11
C11
D8
RN B11
RP A11
GN B12
GP A12
SOG D13
BN B13
BP A13
C10
D12
C12
ADCPLLVDD1
ADCPLLVDD C15
ADCPLLVSS M14
SYSPLLVSS L15
SYSPLLVDD D16
TESTP B14
TESTN A14
XTALVDD C16
XTALO B15
XTALI
A15
XTALVSS M15
APLL_CAP A16
APLLVSS D18
APLLVDD D17
DMPLLVDD C17
DMPLLVSS C18
VI0
B16
VI1
A17
VI2
B17
VI3
A18
VI4
B18
VI5
C19
VI6
D19
DVDD18
E23
VI7
A19
VI8
B19
VI9
C20
VI10
D20
VI11
A20
DVSS3
L16
VI12
B20
VI13
C21
VI14
D21
VI15
A21
DVSS18
M16
VI16
B21
VI17
C22
VI18
D22
VI19
A22
VI20
B22
VI21
C23
VI22
D23
VI23
A23
VCLK_DVI
B23
1
GND

A
1
B
C
D
E
MT8205 ANALOG DECOUPLING&DIGITAL DECOUPLING
DV18A
DV18A 1,2,3 AV33
DV33A
DACVREF
DACVREF 3
DACFS
DACFS 3
ADCPLLVDD1
L7
ADCPLLVDD1 3
ADCPLLVDD
ANALOGVDD
ADCPLLVDD 3
APLLVDD
L6
DV18A
APLLVDD 3
ANALOGVDD
AV33
FOR DACVDD
DACVDD
L12
FB
C8
ANALOGVDD 3
VPLLVDD
DV18A
ADCPLLVDD1
BEAD/SMD/0603
4.7uF
VPLLVDD 3
LVDDA
CE12
FB
C7
CB10
C10
C0603/SMD
LVDDA 3
+
CB11
BEAD/SMD/0603
CE13
4.7uF 0.1uF
FB
0.1uF
GND
+
C0603/SMD C0603/SMD
BEAD/SMD/0603
C24
CB32
R20
ADCVDD
10uF/25v 0.1uF
GND
4.7uF
0.1uF
ADCPLLVDD
ADCVDD 3
DACVDD
10uF/25v
C0603/SMD C0603/SMD
4 DACVDD 3
4
AVCM
DACVDD
0
C13 CB13
AVCM 3
VOCM
+ CE14 4.7uF 0.1uF
VOCM 3
VICM
C9
CB12
GND
22uF/25v C0603/SMD C0603/SMD
VICM 3
4.7uF 0.1uF
VREFP4
C0603/SMD C0603/SMD
GND
VREFP4 3
VREFN4
GND
VREFN4 3
ADCVDD0
ADCVDD0 3
ADCVDD4
DACVDD
ANALOGVDD
ADCVDD4 3
PWM2VREF
PWM2VREF 3
AUXTOP
C14 CB14
C15 CB15
AUXTOP 3
AUXBOTTOM
4.7uF 0.1uF
+ CE15 4.7uF 0.1uF
AUXBOTTOM 3
REXTA
C0603/SMD C0603/SMD
47uF/16v C0603/SMD C0603/SMD
REXTA 3
APLL_CAP
GND
APLL_CAP 3
XTALI
L14
GND
XTALI 3
XTALO
R101 0/NC
ADCVDD0
ADCVDD
XTALO 3
VCC
FB
AVCM
FOR ADCVDD
R0805/SMD
C27
CB36
R22
CB35
4.7uF
0.1uF
APLLVDD
U8 CM1117-3.3V
0.1uF
C0603/SMD C0603/SMD
CB45
ADC_VDD
0
C17 CB20
4.7uF
L8 Vout
GND
GND
+ CE20 4.7uF 0.1uF
GND
3
ADC_VDD
IN OUT
2
22uF/25v C0603/SMD C0603/SMD
PWM2VREF
VOCM
FB
GND
BEAD/SMD/0805
+ CE18
CB17
CB42
CB46
+
+ CE17
10uF/25v CB16
+ CE22
0.1uF
0.1uF
CB18
220uF/16v
0.1uF
47uF/16v C0603/SMD
ANALOGVDD
CE16
0.1uF
SOT223/SMD
0.1uF
GND
100uF/16v
GND
C18 CB22
GND
4.7uF 0.1uF
C0603/SMD C0603/SMD
VICM
GND
CB47
0.1uF
ADJ/GND
3 GND
3
AV33
VREFP4
CB48
4.7uF
C0603/SMD
VREFN4
C0603/SMD
CB44 4.7uF
GND
CB49 4.7uF
C0603/SMD
ADC_VDD
L10
FB
BEAD/SMD/0805
CB24
0.1uF
C0603/SMD
ADCVDD0
GND
ADCVDD0
R23
0
C20
0.1uF
L11
FB
BEAD/SMD/0603
C19
4.7uF
C0603/SMD
VPLLVDD
CB27
0.1uF
C0603/SMD
GND
CB28
0.1uF
CB30
0.1uF
GND
ADCVDD0
DV33A
DIGITAL DECOUPLING
+ CE21
47uF/16v
C21
4.7uF
C0603/SMD
VPLLVDD
CB29
0.1uF
C0603/SMD
GND
CB33
0.1uF
CB43
0.1uF
GND
CB25
0.1uF
CB26
0.1uF
CB31
0.1uF
C22
0.01uF
C23
3300pF
AV33
C25
4.7uF
C0603/SMD
VPLLVDD
CB34
0.1uF
C0603/SMD
GND
2 2
ADCVDD4
R21
0
FB
C26
CB41
DV18A
BEAD/SMD/0603
4.7uF
0.1uF
L9
C0603/SMD
LVDDA
GND
FB
BEAD/SMD/0603
CB19 0.1uF
CB37
CB38
CB39
CB40
CE19
C0603/SMD
0.1uF
0.1uF
0.1uF
0.1uF
+
GND
C0603/SMD C0603/SMD C0603/SMD C0603/SMD
C16
0.1uF
47uF/16v
LVDDA
XTALI
R19
100k
L13
XTALO
DACVREF
APLL_CAP
C33
C32
0.1uF/NC
1500pF
GND
GND
0603 PUT ON NEARLY BGA
C28
3300pF
C0603/SMD
C29
3300pF
C0603/SMD
C30
3300pF
C0603/SMD
C31
3300pF
C0603/SMD
CB21 0.1uF
C0603/SMD
GND
LVDDA
Y1
C11
33pF
27MHz
C12
33pF
GND
REXTA
DACFS
R24 3.3k
R27 560
GND
GND
0603 PUT ON NEARLY BGA
CB23 0.1uF
C0603/SMD
GND
TP5
LVDDA
L15
FB
R25 50/47R
AUXTOP
TP6
1 1
R26 50/47R
AUXBOTTOM
Title
Size Doc Number R e v
C
MT8205 DECOUPOMG--ANALOG V1.2
Wednesday, October 12, 2005
Date: Sheet o f
4 15
A
B
C
D
E

A
1
B
C
D
E
SDV25
SDV25
U9
F_A1 25
F_D0
D1V25
F_A2
A0
D0
29
RN1
U10
24
F_D1
A_DQS[0..3] A_DQS[0..3] 3
A_RA3
D_RA3
F_A3
A1
D1
31
7 8
1
F_D2
A_RA[0..11] A_RA[0..11] 3
A_RA2
D_RA2
D_DQ0
VDD VSS 66
23
D_DQ15
F_A4
A2
D2
33
5 6
2
RN2
F_D3
A_BA[0..1] A_BA[0..1] 3
A_RA1
D_RA1
DQ0 DQ15
65
22
D_RA0
F_A5
A3
D3
35
3 4
3
F_D4
A_DQM[0..1] A_DQM[0..1] 3
A_RA0
D_RA0
D_DQ1
VDDQ VSSQ 64
7 8
21
D_DQ14
D_RA1
F_A6
A4
D4
38
1 2
4
F_D5
A_DQ[0..31] A_DQ[0..31] 3
D_DQ2
DQ1 DQ14
63
5 6
20
D_DQ13
D_RA2
F_A7
A5
D5
40
5
3 4
19
F_D6
D_RA3
F_A8
A6
D6
42
RN3 22x4
DQ2 DQ13
62
6
F_D7
A_CLK
A_CLK 3
A_RA4
D_RA4
D_DQ3
VSSQ VDDQ 61
1 2
18
D_DQ12
F_A9
A7
D7
44
7 8
7
A_CLK#
A_CLK# 3
A_RA5
D_RA5
D_DQ4
DQ3 DQ12
60
8
D_DQ11
F_A10
A8
D8
30
5 6
8
75x4
A_CKE
A_CKE 3
A_RA6
D_RA6
DQ4 DQ11
59
7
F_A11
A9
D9
32
3 4
9
RN4
DV33A
A_CS#
A_CS# 3
A_RA7
D_RA7
D_DQ5
VDDQ VSSQ 58
6
D_DQ10
D_RA4
F_A12
A10
D10
34
1 2
10
A_RAS# A_RAS# 3
D_DQ6
DQ5 DQ10
57
8
7
5
D_DQ9
D_RA5
F_A13
A11
D11
36
11
6
5
4
A_CAS# A_CAS# 3
D_RA6
F_A14
D12
39
RN5 22x4
DQ6 DQ9
56
A12
12
DV33A
A_WE#
A_WE# 3
A_RA8
D_RA8
D_DQ7
VSSQ VDDQ 55
4
3
3
D_DQ8
D_RA7
DV33A
F_A15
A13
D13
41
7 8
13
2
SDV25
SDV25 3
A_RA9
D_RA9
F_A16
D14
43
R28
DQ7 DQ8
54
2
1
A14
5 6
14
F_A0
4 4
VREF
VREF 3
A_RA11
D_RA11
NC
NC 53
1
F_A17
A15
D15
45
3 4
15
75x4
F_A19
RWR#
PWR# 13
D_DQS0
VDDQ VSSQ 52
48
D_DQS1
F_A18
A16
A18
16
1 2
16
17
R29
PCE#
PCE# 3
A17
NC 13
10k
LDQS UDQS 51
RN6
17
15
0
F_OE#
F_OE# 3
22x4
NC
NC 50
2
1
VREF
D_RA11
F_A20
RY/BY WP/ACC 14
18
R30
9
F_D[0..7] F_D[0..7] 3
A_RA10 R31 22 D_RA10
VDD VREF
49
4
3
D_RA9
A19 BYTE
Del By Ada
47
19
10
F_A[0..20] F_A[0..20] 3
D_DQM0
DNU VSS 48
6
5
D_DQM0
CB50
D_RA8
PCE#
A20
20
26
FLASHVCC
D_WE#
LDM UDM 47
8
7
D_CLK#
10k
F_OE#
CE
VCC 37
21
28
RN7
D_CAS#
WE
CK 46
D_CLK
PWR#
OE
22
11
A_DQ0
D_DQ0
D_RAS#
CAS
CK 45
75x4
D_CKE
0.1uF
WE GND1
27
7 8
23
A_DQ1
D_DQ1
D_CS#
D_RA10 R32 75
GND2
46
CB51
RAS CKE 44
5 6
24
DV33A
12
0.1uF
A_DQ2
D_DQ2
CS
NC 43
RESET
3 4
25
A_DQ3 1 2 D_DQ3
D_BA0
NC
A12
42
26
D_RA11
D_BA1
BA0
A11
41
27
D_RA9
RN8
MX29LV160BT
RN9 47x4
D_RA10
BA1
A9
40
28
D_RA8
D_DQ0 7 8
TSOP 48 pin
A_DQ4 7 8 D_DQ4
D_RA0
A10/AP A8
39
29
D_RA7
D_DQ1 5 6
A_DQ5 5 6 D_DQ5
D_RA1
A0
A7
38
30
D_RA6
D_DQ2 3 4
D1V25
A_DQ6 3 4 D_DQ6
D_RA2
A1
A6
37
31 8M x 16
D_RA5
D_DQ3 1 2
A_DQ7 1 2 D_DQ7
D_RA3
A2
A5
36
32
D_RA4
D1V25
A3 DDR A4
35
33
75x4
RN10 47x4
VDD
RN11
A_DQ8 7 8 D_DQ8
M13L128168 8Mx16-6
D_DQ4 7 8
A_DQ9 5 6 D_DQ9
D_DQ5 5 6
CB52 CB53 CB54 CB55 CB56 CB57 CB58 CB59 CB77
A_DQ10 3 4 D_DQ10
D_DQ6 3 4
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A_DQ11 1 2 D_DQ11
D_DQ7 1 2
RN12 47x4
75x4
A_DQ12 7 8 D_DQ12
RN13
A_DQ13 5 6 D_DQ13
D_DQ8 7 8
A_DQ14 3 4 D_DQ14
D_DQ9 5 6
D1V25
A_DQ15 1 2 D_DQ15
D_DQ10 3 4
D_DQ11 1 2
47x4
SDV25
SDV25
75x4
CB60 CB61 CB62 CB63 CB64 CB65 CB66 CB67 CB78
RN14
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RN15
U11
D_DQ12 7 8
A_DQ16 7 8 D_DQ16
1
D_DQ13
A_DQ17
D_DQ17
D_DQ16
VDD VSS 66
5 6
5 6
2
D_DQ31
D_DQ14
3 A_DQ18
D_DQ18
DQ0 DQ15
65
3 4
3 4
3
D_DQ15
3
A_DQ19
D_DQ19
D_DQ17
VDDQ VSSQ 64
1 2
1 2
4
D_DQ30
D_DQ18
DQ1 DQ14
63
5
D_DQ29
75x4
D1V25
DQ2 DQ13
62
RN16 47x4
6
A_DQ20
D_DQ20
D_DQ19
VSSQ VDDQ 61
RN17
7 8
7
D_DQ28
D_DQ16
A_DQ21
D_DQ21
D_DQ20
DQ3 DQ12
60
2
1
5 6
8
D_DQ27
D_DQ17
A_DQ22
D_DQ22
DQ4 DQ11
59
4
3
3 4
9
D_DQ18
CB68
CB71
CB74
CB76
A_DQ23
D_DQ23
D_DQ21
VDDQ VSSQ 58
6
5
CB69 CB70
CB72 CB73
CB75
1 2
10
D_DQ26
D_DQ19
0.1uF
0.1uF
0.1uF
0.1uF
D_DQ22
DQ5 DQ10
57
8
7
0.1uF 0.1uF
0.1uF 0.1uF
0.1uF
11
D_DQ25
RN18
DQ6 DQ9
56
47x4
12
A_DQ24
D_DQ24
D_DQ23
VSSQ VDDQ 55
75x4
7 8
13
D_DQ24
A_DQ25 5 6 D_DQ25
DQ7 DQ8
54
RN19
14
D_DQ20
A_DQ26 3 4 D_DQ26
NC
NC 53
2
1
15
D_DQ21
D1V25
A_DQ27 1 2 D_DQ27
D_DQS2
VDDQ VSSQ 52
4
3
16
D_DQS3
D_DQ22
LDQS UDQS 51
6
5
17
D_DQ23
RN20 47x4
NC
NC 50
8
7
18
VREF
+ CE24
A_DQ28 7 8 D_DQ28
VDD VREF
49
C34
19
C35
C38 C39 C40
A_DQ29 5 6 D_DQ29
D_DQM1
DNU VSS 48
75x4
3300pF
C36 C37
C41
20
D_DQM1
220uF/16v
3300pF
3300pF 3300pF 3300pF
A_DQ30 3 4 D_DQ30
D_WE#
LDM UDM 47
CB79
RN21
3300pF 3300pF
3300pF
21
D_CLK#
D_DQ27
A_DQ31 1 2 D_DQ31
D_CAS#
WE
CK 46
1 2
22
D_CLK
D_DQ26
D_RAS#
CAS
CK 45
3 4
23
D_CKE
D_DQ25
47x4
D_CS#
RAS CKE 44
0.1uF
5 6
24
D_DQ24
CS
NC 43
7 8
25
D_BA0
NC
A12
42
26
D_RA11
A_DQS0
D_DQS0
D_BA1
BA0
A11
41
75x4
R33 47
27
D_RA9
D_RA10
BA1
A9
40
RN22
28
D_RA8
D_DQ31
A_DQS1 R34 47 D_DQS1
D_RA0
A10/AP A8
39
1 2
29
D_RA7
D_DQ30
D_RA1
A0
A7
38
3 4
30
D_RA6
D_DQ29
A_DQS2
D_DQS2
D_RA2
A1
A6
37
5 6
R35 47
31 8M x 16
D_RA5
D_DQ28
D_RA3
A2
A5
36
7 8
32
D_RA4
DDR
A_DQS3
D_DQS3
A3
A4
35
R36 47
33
VDD VSS 34 75x4
SDV25
M13L128168 8Mx16-6/NC FOR ENTRY
RN23
D_RAS# 7 8
D_CS# 5 6
SDV25
SDV25
RN24
D_BA0 3 4
A_CS# 7 8 D_CS#
D_BA1 1 2
A_RAS# 5 6 D_RAS#
2 2
A_CAS# 3 4 D_CAS#
75x4
CB80 CB81 CB82 CB83 CB84 CB85 CB86 CB87
A_WE# 1 2 D_WE#
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R41 4.7k
22x4
D_DQS2 R37 75
A_BA1 R38 22 D_BA1
D1V25
U12
SDV25
1
D_DQS3 R39 75
A_BA0 R40 22 D_BA0
GND VTT
8
2
D1V25
SD PVIN 7
3
D_CAS# R42 75
SDV25
A_DQM0 R43 22 D_DQM0
VREF
VSENSE AVIN 6
4
TP7
VREF VDDQ 5
D_WE# R44 75
A_DQM1 R45 22 D_DQM1
IC LP2996 DDR Termination SOP8 + CE25
CB91 CB92 CB93 CB94
47uF/16v
D_DQM1 R46 75
CB88 CB89 CB90
A_CKE R47 22 D_CKE
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
CB95 CB96 + CE26
D_DQS1 R48 75
A_CLK R49 22 D_CLK
220uF/16v
0.1uF 0.1uF
D_DQS0 R50 75
A_CLK# R51 22 D_CLK#
D_DQM0 R52 75
SDV25
SDV25
VSS 34 C42
3300pF
C43
3300pF
C44
3300pF
C45
3300pF
C46
3300pF
C47
3300pF
C48
3300pF
C49
3300pF
VREF
VREF
VREF
CB105
0.1uF
CB106
0.1uF
CB107
0.1uF
SDV25
CB108
0.1uF
VREF DECOUPLING
CB109
0.1uF
VCC
+ CE31
220uF/16v 220uF/16v 220uF/16v 220uF/16v
1 VREF
SOT223/SMD
1
220uF/16v
SDV25
U13 CM1117-2.5V
L16
3
IN OUT
2
FB
BEAD/SMD/0805 + CE27
+ CE28
+ CE29
+ CE30
ADJ/GND
CB97
0.1uF
CB98
0.1uF
CB99
0.1uF
CB100
0.1uF
CB101
0.1uF
CB102
0.1uF
CB103
0.1uF
CB104
0.1uF
CB110
CB111
CB112
CB113
CB114
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size Doc Number R e v
C
DDR MEMORY&FLASH V1.2
Wednesday, October 12, 2005
Date: Sheet o f
5 15
A
B
C
D
E

A
B
C
D
E
VGA_IN_L
VGA_IN_L 12
VGA_IN_R
VGA_IN_R 12
P2
HSYNC_VGA
HSYNC_VGA 3
VGAVSYNC#
VGAVSYNC# 3
RED_GND
R
RED_GND 8
1
VGA_R R56 15K
VGA_IN_R
GRN_GND
GRN_GND 8
2
BLU_GND
BLU_GND 8
3
RED
4 L
RED 8
VGA_L
VGA_IN_L
GREEN
4
4
R58 15K
GREEN 8
PHONEJACK STEREO
G
BLUE
BLUE 8
RSRXD
RSRXD 1
PHONEJACK/DIP
RSTXD
RSTXD 1
R59 R60
K1
K2
K3
K4
K5
75K
75K
Change by MICO
VSYNC#
L17
VGAVSYNC#
Change by MICO
FB
BEAD/SMD/0603 R61
D13
2.2k C50
HSYNC#
0.1uF
SOT23/SMD VCC
Modified by Bin_wang.22/7/05
D16
RED_GND
SOT23/SMD
L18
VCC
GREEN
GND
HSYNC#
HSYNC_VGA
3 3
D14
FB
VSYNC#
VCC
BEAD/SMD/0603 R62
2.2k C51
D17
SOT23/SMD
5pF
GRN_GND
SOT23/SMD VCC
BLUE
GND
1
1
2
2
3
3
RED
1
2
2
3
VGA_PLUGPWR
D15
SOT23/SMD
VCC
VGA_PLUGPWR
VGA_PLUGPWR
RSRXD 11
1
RED
6
RED_GND
VCC
VGASDA R55 100 VGA_SDA 12
2
GREEN
CB115
R53 R54
7
GRN_GND DIODE SMD
U14
2 10k 10k
HSYNC# 13
3
BLUE 1N4148/SMD
D2
2
1
BLU_GND
D3
0.1uF
NC VCC 8
8
VSYNC#
RSTXD
DIODE SMD
2
NC WP
7
14
4
VGASCL
VGA_PWR
VGA_PLUGPWR
1N4148/SMD
3
NC SCL
6
9
4
VGASDA
VGASCL R57 100 VGA_SCL
GND SDA
5
15
5
10
EEPROM 24C02
GND
16
P3
D-SUB15 FEMALE
DSUB15/DIP/F
BLU_GND
1
3
17
1
2
3
1 1
Title
Size Doc Number Rev
B
VGA IN&PC AUDIO IN V1.2
A
B
C
D
Date: Wednesday, October 12, 2005 Sheet 6 o f 15
E

A
5
3
4
6
6
5
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
B
C
D
E
Y
Y 8
Y_GND
Y_GND 8
CB
CB 8
CB_GND
CB_GND 8
CR
TU_VCC
C122 4.7nF Y1SOY
CR 8
CR_GND
J5
COMPONENTS SWITCH.
CR_GND 8
SOY
TU_12V
SOY 3
TUNER IN
SY_IN
1
SY_IN 8
SY_GND1
2
SY_GND1 8
SC_IN
3
Y1_INB
R63 0 Y1B CE32 22uF/10V Y1SWB
VCC
SC_IN 8
SC_GND1
4
VCC
SC_GND1 8
AV2_IN
SDA
5
VCC
VCC
AV2_IN 8,12
AV2_GND
SCL
6
AV2_GND 8
TV
SIF1_OUT
7
R64
R68
TV 8,12
TV_GND
AF1_OUT
8
75
10K
R67
L19
4 TV_GND 8
4
AV1_IN
9
D4
L20
10K
AV1_IN 8,12
AV1_GND
TV_GND
10
BAV99
FB
FB
AV1_GND 8
U16
U15
TV
11
Y1_GNDB
Y1_GNDB
ORO2
GPIO_DVD0
SIF1_OUT
12
1
CB1SWB
S VCC 16
1
GNDS
CBQ
S VCC 16
GNDS
SIF1_OUT 8
2
AF1_OUT
CB2SWB
I0A E#
15
2
CON12
Y1SOY
CB3SWB
SOYQ
AF1_OUT 8
3
SCL
CBQ
I1A I0D 14
I0A E#
15
3
PH12/2.0
Y2SOY
CB
Y3SOY
SCL 1,10
4
SDA
Y1SWB
YA I1D 13
I1A I0D 14
4
SOYQ
YQ
SOY
SDA 1,10
VCC
5
P4
Y2SWB
I0B YD 12
YA I1D 13
5
6
CR1SWB
Y3SWB
CRQ
TUNER_12V
Y2_INB
Y1_INB
CB1_INB
CB1B
CB1SWB
YQ
CR2SWB
Y
CR3SWB
TUNER_12V 1
2 3
R65 0
I1B I0C 11
I0B YD 12
6
CE33 22uF/10V
7
Y1_GNDB
GNDS
YB I1C 10
I1B I0C 11
7
1
8
CRQ
GNDS
CR
OGO[0..6] OGO[0..6] 3,9,13
GND YC 9
YB I1C 10
8
C129
GND YC 9
ORO2
100pF CB2_INB
CB1_INB
ORO2 3
5 6
C117
D5
IDTQS3VH257/TIV330
IDTQS3VH257/TIV330
AV_L
CB1_GNDB
AV_L 12
4
100pF
BAV99 R66
TSSOP16/SMD
TSSOP16/SMD
AV_R
C130
75
AV_R 12
100pF CR2_INB 8 9 CR1_INB
C127
YPBPR1_L
CR1_GNDB
CB1_GNDB
CB1_GNDB
YPBPR1_L 12
7
100pF
YPBPR1_R
C131
YPBPR1_R 12
YPBPR2_L
100pF
RCA1X3 EMC Ready
YPBPR2_L 12
YPBPR2_R
RCA5/9P/Y
C128
VCC
YPBPR2_R 12
DVI_L
P5
100pF
CR1_INB
R69 0 CR1B CE35 22uF/10V CR1SWB
SOYQ R311 0 SOY
DVI_L 12
DVI_R
YPBPR1/R
YPBPR1/L
DVI_R 12
3
1
YQ R312 0 Y
R70
+12V
YPBPR2/R
YPBPR2/L
VCC
+12V 1,10,13,14
4
2
75
J8
D6
CBQ R313 0 CB 9/05
OGO6
RCA2
BAV99
OGO6 3
GPIO_DVD0 GPIO_DVD0 3
1 DVI/R
RCA2X2/6P/DIP
R272
CRQ R314 0 CR
GPIO
GPIO 3,10
2 GND
CR1_GNDB
CR1_GNDB
47k
CE82
GPIO_DVD2 GPIO_DVD2 3
3 DVI/L
IR
IR 3,11
4 GND
AV1_L
VCC
4x1 W/HOUSING
P7
P6
C123 4.7nF Y2SOY
R274VCC
VCC
DIP4/W/H/P2.0
DVI/L
AV1_IN
22uF/25v
1
1
47k
2
VCC
2DVI/R
C52
L22
3 AV1_R
100pF
R275
VCC
TU_VCC
4 AV1_L
Y2_INB R71 0 Y2B CE37 22uF/10V Y2SWB
47k
CE83
RCA2
Change by MICO
L21
3 FB
CE41
RCA2/4P/DIP
5 AV1_GND
AV1_R
FB
3
+
6
D7
R72
C53
BAV99
VCC R276
1000uF/16v 0.1uF
RCA1X3
22uF/25v
47k
75
RCA2X2/6P/DIP
Y1_GNDB
Y2_GNDB
J6
R277
AV1 & S-VIDEO AUDIO IN
47k
R299 R300
CB116
CE84
TUNER_12V
1 AV2_IN
10K
0.1uF
2 AV2_GND
VCC
AV2_L
10K
L23
3 AV2_L
TU_12V
4 AV2_R
CB2_INB
R74 0 CB2B CE39 22uF/10V CB2SWB
R278
U17
22uF/25v
47k VCC
12
FB
+ CE42
4x1 W/HOUSING
0X VCC 16
1
1000uF/16v C54
DIP4/W/H/P2.0
D8
R75
0Y
AV/R
JP1
14
0.1uF
BAV99 75
1X Y 3
5
AV/L
CON\SVHS
R279
1Y X 13
15
SC_IN 2
3 SY_IN
CB1_GNDB
CB2_GNDB
47k
2X
CE85
2
SC_GND1 1
4SY_GND1
2Y
11
AV2_R
3X INH 6
4
7
5
VCC
VCC
OGO6
3Y
10
R280
GPIO_DVD0
A VEE 7
VCC
22uF/25v
9
47k
B VSS 8
CR2_INB
R76 0 CR2B CE40 22uF/10V CR2SWB
CD 4052BC
R281
SOP16/SMD
47k
CE86
R11
J7
VCC
10k/NC
D9
R77
DVD/L
ADD BY MICO
DVD/R
1
BAV99 75
VCC
8/18 modify by steven
DVD/L
2
R282
R12
3
CR1_GNDB
CR2_GNDB
22uF/25v
47k
AV1_L R350 0/NC AV/L
10k
DVD_IR
4
DVD/CB_GND
5
R283
AV1_R R351 0/NC AV/R
DVD/CB_IN
VCC
47k
R107 SOT-23
6
CE87
4.7K DVD/Y_GND
7
C124 4.7nF
Y3SOY
GPIO_DVD2
2N3904
1
DVD/Y_IN
8
DVD/R
Q3
DVD/CR_GND
9
DVD/CR_IN
10 10x1 W/HOUSING
R285
22uF/25v
47k
2 2
PH10/2.0
DVD/Y_IN
R78 0 Y3BCE34
22uF/10V Y3SWB
IR
R79
75
D10
BAV99
Y_GND
FB5 0
DVI/R 15K
R86 DVI_R
DVD/Y_GND
Y3_GNDB
CB_GND FB4 0
DVI/L 15K
R84 DVI_L
CR_GND FB3 0
VCC
YPBPR2/R15K
R97 YPBPR2_R
+12V
DVD/CB_IN
R85 0 CB3B CE36 22uF/10V CB3SWB
YPBPR2/L 15K
R94 YPBPR2_L
NEARLY YPBPR2-CON.
Y2_GNDB
CB2_GNDB
CR2_GNDB
Y1_GNDB
CB1_GNDB
CR1_GNDB
FB6 0
FB7 0
FB10 0
FB11 0
FB12 0
FB13 0
NEARLY YPBPR1-CON.
2 3
AV/R
AV/L
15K
15K
YPBPR1/R15K
YPBPR1/L15K
R103
R102
R92
R87
AV_R
AV_L
YPBPR1_R
YPBPR1_L
R118
75K
R119
75K
R120
75K
R121
75K
R122
75K
R123
75K
R124
75K
R125
75K
DVD/CB_GND
DVD/CR_IN
DVD/CR_GND
VCC
R98 0
VCC
D11
BAV99
D12
BAV99
R89
75
CR3B CE38
R100
75
22uF/10V
CB3_GNDB
CR3SWB
CR3_GNDB
GPIO
VCC
R269
10K
R95
4.7k
VCC
1
2 3
R267
22K
SOT-23
2N3904
Q2
R268
22K
4
3
2
1
U26
G2
S2
G1
S1
D2
5
D2
6
D1
7
D1
8
IR7314
L48
DVD+5V
FB
BEAD/SMD/1206
DVD+5V
DVD+5V
GND
GND
5
4
3
2
1
J9
5x1 W/HOUSING R.A.
PH5/2.5
1 1
Change by MTK
Title
Size Doc Number R e v
C
VIDEO IN & TUNER IO V1.2
Wednesday, October 12, 2005
Date: Sheet o f
7 15
A
B
C
D
E

A
+
+
B
C
D
E
Y
R128
C55
Y+
VGASOG
RED+
GREEN+
BLUE+
CB+
CR+
Y+
Y-
SY+
CVBS1-
CB-
CR-
GREEN-
RED-
4 4
BLUE-
0
100
BLUE- 3
FB2
47nF
47nF
C62
0
15pF
SY-
SC+
CVBS1
CVBS1+
CVBS0-
SC-
18
22
SC- 3
47nF
R111
R108
CVBS0+
56
C71
R143
C73
CVBS0+ 3
330pF
SY_IN
SY
SY+
CVBS0-
R142
C72
CVBS0- 3
AV2_GND
CVBS2_GND
CVBS2-
22
0
R110
47nF
CVBS1+
FB8
0
75
C74
CVBS1+ 3
47nF
330pF
CVBS1-
0
Close to 8205.
R144
C75
CVBS1- 3
SY_GND1
SY_GND
SY-
CVBS2+
CVBS2+ 3
3 FB9
0
3
CVBS2-
47nF
CVBS2- 3
0
MPX1
MPX2
Y
Y_GND
CB
AV2_IN
AV2_GND
TV
TV_GND
AV1_IN
AV1_GND
SIF1_OUT
AF1_OUT
RED
GREEN
BLUE
RED_GND
GRN_GND
OUTPUT
VGASOG 3
RED+ 3
RED- 3
GREEN+ 3
GREEN- 3
BLUE+ 3
CB+ 3
CB- 3
CR+ 3
CR- 3
Y+ 3
Y- 3
SY+ 3
SY- 3
SC+ 3
MPX1 3
MPX2 3
Y 7
Y_GND 7
CB 7
AV2_IN 7,12
AV2_GND 7
TV 7,12
TV_GND 7
AV1_IN 7,12
AV1_GND 7
SIF1_OUT 7
AF1_OUT 7
RED 6
GREEN 6
BLUE 6
RED_GND 6
GRN_GND 6
TV
TV_GND
AV1_IN
AV1_GND
AV2_IN
R90 18
R80 18
R105
SIF1_OUT
R93
56
R82
56
FB1
0
CVBS0
CVBS0_GND
CVBS1_GND
CVBS2
FROM Tuner
R146 0
R130
22
R132
R135
22
R138
0
R140
R147 8.2K
C80
15pF/NC
C59
330pF
C65
330pF
C57
47nF
C60
C63
C67
C69
47nF
47nF
C81
15pF/NC
CE43
CVBS0+
CR-
CVBS2+
47uF/16v /NC
C78
47nF
MPX1
BLU_GND
L29
47nF
BLU_GND 6
FB
1 1
SC_IN
SC_GND1
GREEN
GRN_GND
BLUE
BLU_GND
L26
L28
R114
FB
BEAD/SMD/0603
Close VGA input interface
0
FB
BEAD/SMD/0603
CB
CB_GND
CR
GREEN_IN
BLUE_IN
Y_GND
CR_GND
R156
75
L27
FB
R159
75
SC
R116
75
SC_GND
FB14
0
C90
5pF
C93
5pF
R145
R148
0
22
C56
15pF
C68
15pF
R155 68
Close to MT8205
100
R131
100
Close to 8205.
R157 100
R158 68
R160 100
R133
R136
100
R137
100
R141
100
C77
330pF
C58
C61
C64
47nF
C66
C70
47nF
47nF
47nF
47nF
C76
C79
4.7nF
C89
C91
C92
C94
47nF
47nF
47nF
47nF
47nF
Y-
CB+
CR+
BLUE-
CB_GND
L24
C83
CB_GND 7
C82
RED
RED_IN
R151 68
RED+
CR
CR 7
FB
R152
CR_GND
BEAD/SMD/0603
47nF
CR_GND 7
47nF/NC
75
SOY
SOY 3,7
CE44
C86
SY_IN
AF1_OUT R149
39k
R150
39k
MPX2
5pF
C87
SY_IN 7
RED_GND
R153 100
RED-
SY_GND1
SY_GND1 7
47uF/16v
C84
C85
L25
47nF
SC_IN
15pF
15pF
2 SC_IN 7
FB
2
C88
SC_GND1
R154 0
VGASOG
SC_GND1 7
CB-
SC+
SC-
GREEN+
BLUE+
GREEN-
INPUT
Title
Size Doc Number R e v
C
AUDIO/VIDEO IN CIRCUIT V1.2
Wednesday, October 12, 2005
Date: Sheet o f
8 15
A
B
C
D
E

A
1
1
+
1
2
3
1
2
1
2
3
4
5
6
7
8
9
3
1
2
3
1
2
3
1
1
2
2
3
3
1
1
2
2
3
3
1
1
2
2
3
3
B
C
D
E
DV33
L31
DVIPWR
DVIPWR
CLOCK+
GND
D29
SOT23/SMD
CLOCK- DDC_SCL DDC_SDA
D30
SOT23/SMD
D31
SOT23/SMD
Add By MTK
D32
SOT23/SMD
VCC VCC VCC VCC
GND
GND
GND
27
25
29
31
33 34
30
32
28
26
R164
100k
FB
+ CE45
100uF/16v
CB117
0.1uF
DVIPWR
DVIPWR
DATA1-
DATA0-
DATA2-
Add By MTK
QO22
75
QO21
74
QO20
73
QO19
72
QO18
71
QO17
70
QO16
69
GND 68
VI[0..23]
VI[0..23]
VCC
DVIODCK
DVIODCK
DVIDE
DVIDE
P8 DVI-I DIP 34P
DIODE SMD
DVIHSYNC
DVIHSYNC
1N4148/SMD
D22
DVIVSYNC
DVIVSYNC
DVIPWR
DVIPWR
DVIPWR
DVIPWR
DVIPWR
DVIPWR
DVIPWR
8205UP1_2
8205UP1_2
DATA2-
1
13
D18
OGO4
OGO4
DATA2+
2
14
DVI_PLUGPWR 1N4148/SMD
DVISCL
DVISCL
3
15
DVISDA
DVISDA
4
16
F_A21
C104 C105
C106 C107
C108 C109
C110 C111
C112 C113
C100 C101
C102 C103
DATA0-
F_A21
5
17
220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v
DDCDVISCL R161 100 DDC_SCL6
18
DATA0+
DDCDVISDA R162 100 DDC_SDA7
19
R163
DVISCDT R167
R DVIPDO#
8
20
10k
4 4
DVICAB R177 0 8205UP1_2
DATA1-
9
21
DATA1+
10
22
11
23
CLOCK+
12
24
CLOCK-
DVICAB
VCC
VCC
VCC
L32
76
GND
GND
GND
DVIPWR
DVIAVCC
OGND
QO1
50
77
DVIPWR
QO23
QO0
49
78
DVIHSYNC0
DATA0+
DATA1+
DATA2+
OVCC
HSYNC 48
FB BEAD/SMD/0603
79
DVIVSYNC0
CB118
DATA2+
AGND
VSYNC 47
80
DVIDE0
C95
C96
DATA2-
RX2+
DE 46
81
10uF/10v 0.1uF
DVIAVCC
RX2-
OGND 45
D36
D37
D38
220pF
82
DVIODCK0
AVCC
ODCK TP8
U18
44
83
AGND
OVCC 43
SOT23/SMD
SOT23/SMD
SOT23/SMD
84
CTL3
VCC
VCC
VCC
DATA1+
AVCC
CTL3
42
TP9
85
OCK_INV
GND
GND
GND
3 DATA1-
RX1+
CTL2
41
TP10
86
HS_DJTR
3
RX1-
CTL1
40
TP11
87
AGND
GND
DVIAVCC
SiI 161B
39
88
AVCC
VCC 38
89
DVI23 CHANGE
DATA0+
AGND
QE23
37
90
DVI22
DATA0-
RX0+
QE22
36
91
DVI21
RX0-
QE21
35
92
DVI20
R165
CLOCK+
AGND
QE20
34
93
DVI19
390
CLOCK-
RXC+
QE19
33
94
DVI18
DVIHSYNC0 2 RN25 1 DVIHSYNC
RXC-
SiI 169
QE18
32
95
DVI17
DVIVSYNC0 4
3 DVIVSYNC
DVIPWR
EXT_RST
AVCC
96
TQFP100/SMD
QE17
31
DVI16
DVIDE0 6
5 DVIDE
DVIPWR
DVIPVCC
EXT_RST
QE16
30
97
DVIODCK0 8
7 DVIODCK
PVCC
OVCC 29
98
33x4
R83
PGND
OGND 28
0/NC
99
DVI15
DVISCL
RESERVED
QE15
27
R170
100
DVI14
R171
L33
OCK_INV
QE14
26
10k
DVI20
2 RN26 1 VI20
10k
DVIPWR
DVIPVCC
DVI21
4
3 VI21
C134
DVI22
6
5 VI22
FB BEAD/SMD/0603
1uF/25V/NC R81
DVI23
8
7 VI23 RED
DVIPD#
DVIPDO#
10k/NC
33x4
C97
C98
DVI16
2 RN27 1 VI16
R344
10uF/10v
220pF
DVI17
4
3 VI17
R176
ADD BY MTK
DVI18
6
5 VI18
R/NC
R/NC
DVIPWR
DVIPWR
DVI19
8
7 VI19
DVI_PLUGPWR
33x4
HS_DJTR
PD#
ST
PIXS
GND
VCC
STAG_OUT
SCDT
PDO
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
OVCC
OGND
OE8
QE9
QE10
QE11
QE12
QE13
DVISTAG
DVISCDT
DVIPDO#
DVI0
DVI1
DVI2
DVI3
DVI4
DVI5
DVI6
DVI7
DVIRST#
DVI12
2 RN28 1 VI12
DVI_PLUGPWR
DVI13
4
3 VI13
DVI_PLUGPWR
CHANGE
DVI14
6
5 VI14
DVI15
8
7 VI15
33x4
GREEN
R310
DVI8
2 RN29 1 VI8
R168 R169
10k
DVI9
4
3 VI9
C99
U19
10k 10k
DVI10
6
5 VI10
1
DVI11
VI11 WHEN USE Sil169//Sil161 ADD R175 , NC R345
0.1uF
NC VCC 8 8
7
2
33x4
NC WP
7
3
DDCDVISCL
2 NC SCL
6
WHEN USE Sil1169 ADD R345,NC R175
2
4
DDCDVISDA
OGO4
DVI4
RN30
VI4
GND SDA 5
R166 0
2
1
DVI5
4
3 VI5
DVIPWR
DVI6
VI6
TP12
6
5
EEPROM 24C02
DVI7
8
7 VI7
33x4
BLUE
R345
DVI0
2 RN31 1 VI0
10k/NC
DVI1
4
3 VI1
DVI2
6
5 VI2
DVIPIXS
DVI_PLUGPWR
DVI3
8
7 VI3
Add by MTK
DVIPWR
33x4
DVIPD#
DVISDA
DVIPIXS
VCC 67
QO15
66
QO14
65
QO13
64
QO12
63
QO11
62
QO10
61
QO9
60
QO8
59
OGND 58
56
OVCC 57
55
54
53
52
51
QO7
QO6
QO5
QO4
QO3
QO2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
M_S#
DVI8
DVI9
DVI10
DVI11
DVI12
DVI13
D33
SOT23/SMD
D34
SOT23/SMD
R175
0
D35
SOT23/SMD
DDCDVISCL
DDCDVISDA
R322
4K7
R323
4K7
2
DV33A
2
DV33A
R88
0/NC
R0603/SMD
DVISCL
DVISDA
F_A21
DVIPWR
DVIRST#
1 1
R91
QF3
QF4
3
3
0/NC
R0603/SMD
MOSFET N 2N7002
SOT23/SMD
MOSFET N 2N7002
SOT23/SMD
R324
4K7
R325
4K7
WHEN USE Sil169/sil1169 ADD
R330 0
R326
10K
R172
0.1uF
When use Sil169//Sil1169 R172 NC,Add R326
WHhen use Sil161 R326 NC,Add R172
M_S#
DVIPWR
R346
10k/NC
R347
10k/NC
When Sil169/Sil161 R346 NC
Add R347
DVISDA
R173
10k/NC
R174
10k/NC
DVISCL
DVISCL REPLACE OCK_INV NET
DVISDA REPLACE ST
WHEN SIL161 ADD R173 R174
WHEN Sil169/ Sil1169 R173 R174 NC
DVIPWR
R327
4.7K/NC
HS_DJTR
R331
0
DVIPWR
R328
4.7K/NC
OCK_INV
R332
0
WHEN USE Sil1169 add R331 R332
WHEN USE Sil169 add R327 R332
WHEN USE Sil161 NC R331 R332
DVIPWR
R329
4k7/NC
DVISTAG
R333
0
When use Sil169/Sil1161 ADD R333
Title
Size Doc Number R e v
DVI INPUT V1.2
C
Wednesday, October 12, 2005
Date: Sheet o f
9 15
A
B
C
D
E

A
1
1
B
C
D
E
+12V
CLK1+
CLK1-
+12V 1,7,13,14
CLK1+ 3
CLK1- 3
5VSB
LVDS OUT(Include PDP and 32' LCD LVDS interface)
DV33A
AP[0..7]
AP[0..7] 3
AN[0..6]
AN[0..6] 3
R
R 3
G
G 3
B
4 B 3
4
VSYNC
VSYNC 3
HSYNC
J10
HSYNC 3
R361 R362 R363
ORO5 Repalce ADIN2
10K 10K 10K
R301 R302 R303 8205UP1_4 Repalce ADIN3
AN0
1
SCL
10K 10K 10K
AP0
SCL 1,7
2
SDA
AN1
SDA 1,7
3
ORO6
AN6 R290 0/NC
AP1
ORO6 3
4
GPIO
ORO5 R291 0/NC CPUGO
AN2
GPIO 3,7
5
+12V
AP6 R292 0/NC
AP2
6
ORO1
8205UP1_4R293
0/NC PDPGO
ORO1 3,14
7
ORO3
CLK1-
ORO3 3,14
8
CLK1+
9
ORO5
+ CE46
AP7 R178 0/NC
AN3
ORO5 3
10
8205UP1_4
220uF/16v
AP3
8205UP1_4 3
11
AN4
12
SCL1
GPIO R179 0/NC SEL_AP7_IRQ
AP4
SCL1 12
13
SDA1
SDA1 12
14
AN5
15
SCL_8205
AP5
SCL_8205 3
16
SDA_8205
+12V
SDA_8205 3
17
VCC
5VSB DV33A
Change by MICO
18
19
5VSB
20
DV33A
R180
R286
21
Change by MICO
4.7k/NC
4.7k
22
23
24
R364 R184
DISPEN_PDWN_READYR185 0
25
F1
10K 10k
SCL_P
R186 100/NC
26
FB L51 BEAD/SMD/1206
L34
4.7k
SDA_P
R187 100/NC
27
FB L52 BEAD/SMD/1206
LVDSVDD
ORO6
1
28
LVDSVDD L49 FB
29
FB
R189
SOT23/SMD
BEAD/SMD/1206
30
4A/?v
2N3904
BEAD/SMD/1206
FUSE/DIP/P10.0 + CE47
Change By MTK Ada
Q4
330uF/25v
FI-SE30P-HF
C330UF25V/D8H14
LVDS/30P/P1.25/S
3 3
+
+
CE48 CE49
CB119 CB120
220uF/16v 220uF/16v 0.1uF 0.1uF
3 2
WHEN USE LG V6 PDP ,ADD R185 R286 ,Must del R193 R194
WHEN USE LG V7 PDP ,ADD R185 R286 R179
WHEN USE SangsungSD1 PDP ,ADD R186 R187 R185 R286
WHEN USE Fujitsu 42 PDP ,ADD R179 R186 R187 R185 R286 R291 R293.REMOVE R178 R290 R292
WHEN NOT USE PDP ADD L49 R178 R290 R292
REMOVE R179 R185 R186 R187 R291 R293
ORO1
ORO3
ORO1 3,14
ORO3 3,14
4.7K REPALAC 47K
2 2
5VSB
DV33A
R
R188 0 SCL1
R195
R181 R182
4.7k 4.7k
R297
75 1%
R183
QF1
0
4.7k
2 3
SCL_8205
R192 0 SCL_P
GND
CRT OUT J11
SCL
MOSFET N 2N7002
G
1
5VSB
DV33A SOT23/SMD
R295 0 SDA1
R
2
R196
G
3
R191
B
4
4.7k
75 1%
QF2
5
R298
HSYNC
6
SDA
2 3
SDA_8205
0
VSYNC
7
GND
8
5VSB
DV33A
MOSFET N 2N7002
R296 0 SDA_P
SOT23/SMD
B
DV33A
GND
R197
R348 R349 R352 R353
75 1%
8x1 W/HOUSING
10K 10K 10K 10K
DIP8/W/H/P2.54
ORO1
R193
0/NC
GND
ORO3
R194
0/NC
CHANGE
1 1
Title
Size Doc Number R e v
C
LVDS/CRT OUT V1.2
Wednesday, October 12, 2005
Date: Sheet o f 10 15
A
B
C
D
E

A
B
C
D
E
OBO[0..7]
OBO[0..7] 3
IR
PWR_GND
INVERTER_PWR
OBO0
OBO1
OBO2
OBO2 3
PWR_GND
4 4
OBO3
OBO3 3
OBO4
OBO5
OBO6
OBO7
8205UP3_0
PWM0
8205UP1_2
PWR_GND
IR 3,7
PWR_GND 1
INVERTER_PWR 1
OBO0 3
OBO1 3
OBO4 3
OBO5 3
OBO6 3
OBO7 3
8205UP3_0 3
PWM0 3,14
8205UP1_2 3,9
PWR_GND 1
VCC
PWM0
R201 4.7k
Inverter_PWR
1
3 2
R199
10k
+ CE50
470uF/50v
Q5
2N3904
SOT23/SMD
R200
100k
Back Light circuit
PANEL INVERTER POWER
+ CE51
470uF/50v
8205UP3_0
CB123
0.1uF
R205
4.7k
1
CB121
0.1uF
VCC
3 2
Inverter_PWR
Dimming
R203
10k
BL_ON/OFF
Q6
2N3904
SOT23/SMD
CB122
0.1uF
Inverter_PWR
PWR_GND
FOR AU 32" INVERTER CONNECTOR
J12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R. ANGLE
14x1 W/HOUSING
DIP14/WH/P2.0/R
SELECT
VCC
R202
R
R204 External PWM input
0
for dimming control
3 3
J13
Inverter_PWR
PWR_GND
L35
FB
BEAD/SMD/1206
1
2
3
4
5
6
7
8
9
10
10x1 W/HOUSING R.A.
DIP10/WH/P2.0/R
R. ANGLE
L36
FB
BEAD/SMD/1206
5VSB
R109 R320 R319R318R317
R316 R315
J19
J14
10K 10K 10K 10K 10K 10K 10K
1
KEYPAD - MAX 8-KEYS
9/05
DIP13/W/H/P2.0
TV/AV
2
13x1 W/HOUSING MENU
3
1
VOL-
4
2 2
OBO0 L37
FB TV/AV 2
VOL+
5
OBO1 L38
FB MENU 3
CH-
6
5VSB
OBO2 L39
FB VOL- 4
CH+
7
OBO3 L40
FB VOL+ 5
8205UP1_2 8
OBO4 L41
FB CH- 6
9
OBO5 L42
FB CH+ 7
IR
8
R206 510
LED_RED
9
CON9
R207
R208
R209 510
LED_GRN
10
10K
10K
8205UP1_2
11
R0603/SMD
R0603/SMD
R210 0 POW
5VSB
12
13
J20
OBO6
R211 4.7K
OBO7
R212 4.7K
1
3 2
Q7
2N3906
1
3 2
Q8
2N3906
IR
LED_RED
LED_GRN
POW
1
2
3
4
5
DV33A
CONN RCPT 5
IR & POWER ON LED
1 1
Title
Size Doc Number R e v
BACK_LIGHT/KEYPAD V1.2
C
Wednesday, October 12, 2005
Date: Sheet o f 11 15
A
B
C
D
E

A
+
+
+
+
+
+
+
+
+
+
+
+
+
B
C
D
E
VGA_IN_L
VGA_IN_R
YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R
DVI_L
DVI_R
SDA1 R218 100
DACBCLK
DACBCLK 3
YPBPR1_R CE57 10uF/25v
R219 100k
DACMCLK DACMCLK 3
CODHPOUTR C125
4 4
DACLRC
DACLRC 3
YPBPR1_L CE59 10uF/25v
R222 100k
HPVDD
C115 C116
DOUT
DOUT 3
100pF 100pF
AOSDATA1 AOSDATA1 3
10uF/10v
AOSDATA3 AOSDATA3 3
AV_R CE60 10uF/25v
R224 100k
CODHPOUTL C126
MUTE
PWM0
+12V
TV
AV_L
AV_R
AV1_IN
AV2_IN
ORO4
ORO7
OGO7
PWM1
SCL1
SDA1
VGA_IN_L 6
VGA_IN_R 6
YPBPR1_L 7
YPBPR1_R 7
YPBPR2_L 7
YPBPR2_R 7
DVI_L 7
DVI_R 7
MUTE 3
PWM0 3,11
+12V 1,7,10,13,14
TV 7,8
AV_L 7
AV_R 7
AV1_IN 7,8
AV2_IN 7,8
ORO4 3
ORO7 3
OGO7 3
PWM1 3
SCL1 10
SDA1 10
DVI_R
DVI_L
YPBPR2_R
YPBPR2_L
AV_L
VGA_IN_R CE64
VGA_IN_L
R215
DACBCLK
DACMCLK
AOSDATA1
DACLRC
DACBCLK
DACMCLK
DOUT
DACLRC
100k
DACLRC
DVDD
SDA14
SCL14
HPVDD
3 10uF/25V R231
3
DV33
CODHPOUTR
GND
10k
L45
TO AUDIO BD
DVDD
CODHPOUTL
DV33
DVDD
FB
+ CE72
47uF/16v
CB130
0.1uF
CE53
CE54
CE55
CE56
CE61
CE65
10uF/25v
10uF/25v
10uF/25v
10uF/25v
10uF/25v
10uF/25v
10uF/25v
R226
R227
R213
R214
R217
R225
100k
100k
100k
100k
100k
100k
R229
1k
1
2
3
4
5
6
7
8
9
10
11
12
U20
AIN2L
AIN1R
AIN1L
DACBCLK
DACMCLK
DIN
DACLRC
ZFLAGR
ZFLAGL
ADCBCLK
ADCMCLK
DOUT
R220 50k
AIN2R 48
AIN3L
47
AIN3R 46
AIN4L
45
AIN4R 44
AIN5L
43
AIN5R 42
AINOPL
41
AINVGL
40
AINOPR 39
AINVGR 38
AGND 37
ADCLRC
DGND
DVDD
MODE
CE
DI
CL
HPOUTL
HPGND
HPVDD
HPOUTR
NC
13
14
15
16
17
18
19
20
21
22
23
24
VCC
TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h
R221 50k
L43
FB
AVDD 36
ADCREFP 35
ADCREFGND 34
VMIDADC 33
AUXL
32
AUXR 31
DACREFP 30
DACREFN 29
VMIDDAC 28
VOUTR 27
VOUTL
26
NC 25
WM8776
C114
+
10uF/25v
HPVDD
VMIDADC
HPVDD_
COD_VOUTR
COD_VOUTL
R14
33
ADCREFP
HPVDD
CB124
0.1uF
+ CE62
10uF/25v
VMIDDAC
+ CE70
10uF/25v
CB125
0.1uF
SCL1
VMIDADC
CB128
0.1uF
COD_VOUTR
COD_VOUTL
R216 100
ADCREFP
+ CE69
10uF/25v
CE71
CE73
10uF/25v
SCL14
SDA14
CB127
0.1uF
R232
10k
+ CE67
10uF/25v
AUSPR
AUSPL
CB126
0.1uF
Change
GND
5VSB
10uF/10v
R230
10k
GND
GND
AUSPR
GND
GND
AUSPL
MUTE
MUST USE SHIELD CABLE
1
2
3
4
5
6
7
8
J15
CON8
A/V Bypass
VCC
R233
0
R0805/SMD
FB15 FB
DACVA
BEAD/SMD/0805
CB131
+ CE74
CB132
0.1uF
VCC
2 100uF/16V
2
1uF
+ CE75
100uF/16V
AUDIO BYPASS.
R334
10K
R10
10k
OGO7 Repalce ADIN0 -----MTK
PWM1 Repalce ADIN1 -----MTK
J16
AOSDATA3
DACBCLK
DACLRC
DACMCLK
R234 33
R235 33
R236 33
R237 33
VCC
1
2
3
4
U22
SDATA
DEM#/SCLK
LRCK
MCLK
AOUTL
8
VA 7
AGND 6
AOUTR 5
CS4334 2-CH AUDIO DAC
SOP8/SMD
L_BYPASS
DACVA
R_BYPASS
R13 0 V_BYPASS 1
OGO7
LINE_MUTE 2
PWM1
3
SPK SWICTH(PDP) BY MICO 4
L_BYPASS 5
R_BYPASS 6
5x1 W/HOUSING
PH6/2.0
TV
AV1_IN
R306
10K
C118 1uF
ORO4
ORO7
C119 1uF
R307
10K
1
2
3
4
U23
IN1 OUT
8
A VCC 7
B IN3
6
IN2 GND 5
BA7612F
CE76
220uF/16v R238 43,1%
VCC
AV2_IN
R239
75
V_BYPASS
R240
75/NC
R241
75/NC
1 1
Title
Size Doc Number R e v
WM8776/WM8766/AUDIO CODEC V1.2
C
Wednesday, October 12, 2005
Date: Sheet o f 12 15
A
B
C
D
E

A
B
C
D
E
+12V
TXD
RXD
DVIVSYNC DVIVSYNC 3,9
VCC
DVIHSYNC DVIHSYNC 3,9
U24
J17
DVIDE
DVIDE 3,9
5V
8
DVIODCK DVIODCK 3,9
D1
S1
1
7
8205UP1_3 8205UP1_3 3
12V
D1
G1
2
1
6
+12V
12V
D2
S2
3
2
5
3
4 D2
G2
4
4
GND
4
DACMCLK
DACMCLK 3,12
CE77
CE78
5
DACBCLK
DACLRC
DACBCLK 3,12
+
CB133 +
IRF7314
6
DACLRC 3,12
0.1uF
CB134
SOIC8/SMD
5V
7
220uF/16v
220uF/16v 0.1uF
8
READY#
REQUEST#
OGO4
OGO5
OGO6
VI[0..23]
+12V 1,7,10,14
TXD 1,3
RXD 1,3
READY# 3
REQUEST# 3
OGO4 3,9
OGO5 3
OGO6 3,7
VI[0..23] 3,9
DV33A
R338
0/NC
5VSB
R339
0/NC
LO = > DTV BOARD POWER ON
HI = > DTV BOARD POWER OFF
DV33A
+12V
OGO3
OGO3 3
OGO1
R244
OGO1 3
U30 74LVC244A
OGO2
OGO2 3
10k
OGO0
U28
OGO4
OGO0 3
20
SW
VCC 2G 19
SW 3
10
PCRXD
TXD
GND 1G 1
PCRXD 1
PCTXD
1 14
TXD_2
OGO3
PCTXD 1
2 13
3
OGO1
2Y4 2A4
17
WE#
RXD_2
3 12
5
C121
OGO2
2A3
15
R245
C120
2Y3
J18
WE# 3
PWR#
4 11
7
RXD
OGO5
1uF
OGO0
2A2
13
1uF
2Y2
PWR# 5
5 10
1 Q9
9
2A1
11
2N3904
2Y1
TXD_0 1
3 GND
6 9
0
SOT23/SMD
VI0
12
RXD_0 2
3
7 8
VI1
1Y4 1A4
8
14
RXD_2
VI2
1Y3 1A3
6
16
TXD_2
VI3
1Y2 1A2
4
74HCT04A/NC
18
1Y1 1A1
2
WE#
REQUEST#
CON50
1 14
2 13
WHEN OGO4 HIGH , DVI OUPUT
3 12
SW
4 11
SW
Function
R256
WHEN OGO4 LOW ,ATSC OUPUT
PWR#
5 10
PC MT5351 U0
Q11
REQUEST0#
6 9
1
0
2N3904
7 8
MT5351 U2 MT8205
ADD 22/9
SOT23/SMD
0/NC
1 PC MT8205
1
74LVC00A/NC
1
PC -----> MT5351 U0RX
3 2
R242
22k
R243
22k
3 2
DV33A
Trace width of 12V>30mil
Trace width of 5V >40mil
"GND Need Very Strong"
DIP8/W/H/P2.54
TXD_0:MT5351 Transmit
RXD_0:MT5351 Receiver
TXD_2:MT5351& MT8205 Communication
RXD_2:MT5351& MT8205 Communication
3
4
5
Add by MTK
6
U31 74LVC244A
7
20
VCC 2G 19
8
10
GND 1G 1
9
10
VI4
3
VI5
2Y4 2A4
17
11
5
VI6
2Y3 2A3
15
12
7
VI7
2Y2 2A2
13
13
9
2Y1 2A1
11
14
15
DV33A
VI8
12
VI9
1Y4 1A4
8
16
14
VI10
1Y3 1A3
6
17
16
VI11
1Y2 1A2
4
18
18
1Y1 1A1
2
19
20
U32 21
DV33A
74LVC244A
22
20
VCC 2G 19
23
10
24
DV33A 5VSB
R246
GND 1G 1
25
5VSB DV33A
10k
R247
VI12
3
VI13
2Y4 2A4
17
26
10k
5
VI14
2Y3 2A3
15
27
7
R248
READY#
VI15
2A2
13
28
R249
2Y2
9
2Y1 2A1
11
29
10k 10k/NC
30
5VSB DV33A
VI16 12
VI17
1Y4 1A4
8
31
14
SW
VI18
1A3
6
32
R250
1Y3
16
Q10 1
READY0#
VI19
1Y2 1A2
4
33
18
2N3904
1Y1 1A1
2
34
35
2 2
R251
L46 L47
SOT23/SMD
0/NC
U33 36
0
FB/NC FB
74LVC244A
37
R252 R253
MTK Modify
20
VCC 2G 19
38
10k/NC 10k JP3
10
GND 1G 1
39
U25
40
2
1
VI20
TXD_2
S VCC 16
3
2
VI21
2Y4 2A4
17
41
1
3
PCTXD
I0A E#
15
5
3
PCTXD
VI22
RXD
I1A I0D 14
2Y3 2A3
15
42
7
4
DV33A
VI23
RXD_2
YA I1D 13
2Y2 2A2
13
43
3x1
9
5
RXD_0
PCRXD
I0B YD 12
2Y1 2A1
11
44
JP3/DIP/P2.54
45
6
PCRXD
DV33A
DVIHSYNC
8205UP1_3
TXD
I1B I0C 11
12
7
DVIVSYNC
READY0#
YB I1C 10
1Y4 1A4
8
46
14
8
TXD_0
DVIDE
REQUEST0#
GND YC 9
1Y3 1A3
6
47
16
DVIODCK
1Y2 1A2
4
48
R254
18
IDTQS3VH257
1Y1 1A1
2
49
10k
R255
50
U29
DV33A
TSSOP16/SMD
10k
3 2
C135
56pF
Title
Size Doc Number Rev
Custom ATSC INTERFACE V1.2
Date: Wednesday, October 12, 2005 Sheet 13 o f 15
A
B
C
D
E

A
B
C
D
E
4 DV33A
4
+12V
ORO1
ORO3
PWM0
ADIN4
ADIN4
+12V 1,7,10,13
ORO1 3,10
ORO3 3,10
PWM0 3,11
ADIN4 3
TP3
RELAY_ON
5VSB
GND
VS_ON
5VD
R287
4.7k/NC
RELAY_ON
DIP7/P2.0
DEL ACD Net--------MTK
R288
10k/NC
3 3
5VD
CN2
1
2
3
4
5
6
7
Change--------MTK
R340
4.7k
R343
10k
PWM0
VS_ON
DV33A
R260
1k
5VSB
5VSB
DV33A
R354
10K
3 2
USE WHEN LG V6
1k
R262
Q16
Q13
1
2N3904
2N3904
2 2
1 R358 1k ORO3
R294
4.7k/NC
R257
1k
3 2
2N3904 1
Q12
3 2
1k
R259
R356
DV33A
R357
10K
Q15
2N3904
0/NC
3 2
1
R355
1k
ORO1
R289
10k/NC
VCC +12V
R360
0/NC
USE WHEN LG V6
+ CE80
+ CE79
220uF/16v
220uF/16v
C220UF16V/D6H11 C220UF16V/D6H11
1 1
Title
Size Doc Number Rev
A
PDP interface V1.2
A
B
C
Date: Wednesday, October 12, 2005 Sheet 14 o f 15
D
E

A
B
C
D
E
From V0.1 To V1.2 change item:
4 4
1,Add R109-10K;R107-4.7K;C135-56pF;0603-R88,R91,R104,R106-0 欧 姆 .0805-R96,R99,R101-0欧 姆
2,Reset IC
增 加 5V Supply;DVI AUDIO ADD CONNECTOR J8.
3,ADIN4 CHANGE TO PWM0
3 3
2 2
1 1
Title
Size Doc Number Rev
A
History
V1.2
A
B
C
Date: Wednesday, October 12, 2005
Sheet 15 o f 15
D
E

AF1_IN
VCC
TU_SCL
TU_SDA
SIF1_IN
AF1_IN
SIF1_IN
TU_SCL
TU_SDA
1C2
47pF
CE7
33uF/16V
1C4
+
10nF
AF1
TU1
1R5 100
1R6
100
1C3
47pF
1
2
3
4
5
6
7
8
9
10
11
1R9 0
AF1
SIF1
SIF1_IN
FQ1236-MK3
1C7
820pF/560pF
12
13
14
1
2
1C5
TU_CVBS
1L3
1.5uH/1.2uH
AF1_OUT
SIF1_OUT
SIF1_OUT
1NF(22P/27P)
1L2
3.3UH(47uH/22uH)
1C8
820pF/560pF
TU_12V
TU_VCC
TU_CVBS
1
2
1C6
1L4
1.5uH/1.2uH
10nF
1
2
1
2
1R1
18
1R7
1.8K
1R10
220
1
2
1
1 2
2
1
1 2
2
1R8
1k
1R11
0R
1R12
82R
1
2
1R3
56
FB2
0
1
2
TU_12V
1C9
NC
1
2
+ CE3
100uF/16V
+ CE8
100uF/16V
1
2
1C1
+ CE6
10uF/25v
1
2
CB6
0.1uF
10nF
1L5
1L6
TV
CB3
0.1uF
TV_GND
SIF1
FB
FB
1
CE4
+
100uF/16V
2
1
2
CE5
+
1
2
1
2
600 OHM
100uF/16V
1
2
FB1
0
SIF_12V
MUTE
AUDPR
AUDPL
Audio Input
CB4
0.1uF
+ CE9
220uF/16V
1
2
1
2
CB5
0.1uF
SDA
SCL
SIF1_OUT
AF1_OUT
TV_GND
TV
J1
J6
4x1 W/HOUSING
CB7
0.1uF
1J1
CON12
4x1 W/HOUSING
1
2
L1
2mH
+
C23
1000UF/35V
AUSPL
AUSPR
1
2
+
J8
NS
C60
10UF
X5R
C59
10UF
X5R
R70
5%
0R/NC
C57
1000UF/35V
M1
1
R48 1k8
5%
R53
100K
5%
R56
1k8
5%
R60
100K
5%
GND HOLE
1
2
1
2
R49 4K7
5%
C45
1n
C47
1n
R57
4K7
5%
AUDPL
C20
10UF
AUDPR
1
2
1
2
C40
10UF
R50
C46
1n
R58
4K7
5%
C48
1n
4K7
5%
M2
1K8
5%
R4
5%
100K
1K8
5%
R19
5%
100K
1
R51
R52
1 2 3 4 5 6 7 8
R54
C22
4K7
5%
C54
1n
22U/16V
R59
4K7
5%
R64
47K
5%
GND HOLE
C52
1n
4K7
5%
47K
4K7
5%
10K
5%
5%
R62
10K
5%
C44
22U/16V
C14
22UF/16V
4K7
5%
C55
1n
R55
U5A
RC4558
22P
U5B
RC4558
22P
C53
1n
C19
22UF/16V
4K7
5%
R63
10K
5%
10K
5%
1
5%
2
R10
10K
4K7
5%
1
5%
2
1
5%
2
R37
10K
4K7 5%
C2
100U/35V
C43
1
5%
2
10U/16V
R11
10K
1
2
C26
10U/16V
M3
U2A
R36
10K
C13
100N
1
C24
22pF
U2B
5%
C41
22pF
47K
R38
5%
47K
5%
47K
5%
GND HOLE
C12
100NF
RC4558
RC4558
1
2
+
C10
100UF/25V
+24V
C31
1UF
X5R
C3
R65
47K
5%
R61
47K
5%
1UF
X5R
5%
R18
10K
3K3 5%
C56
100NF
X7R
M4
1
R3
5%
10K
1
2
R32
0R
5%
GND HOLE
1
2
R68
NC/0R
5%
5%
MUTEC
MUTEC
R5
100K
5%
R17
100K
R21
5%
10K
R44
R7
5%
10K
0
NPO
4.7nF
C8
5%
NPO
4.7nF
C30
82K
C1
22pF
5%
R1
1
2
C15
NC
C21
22pF
5%
R14
82K
1
2
C34
NS
A
NPO
C5
4.7uF
X5R
U1
NPO
ATA-120
C27
4.7uF
X5R
U3
R2
ATA-120
R16
R30
10k
R43
4K7
1
2
+
C42
100UF/25V
D7
4.7V
1
2
C6
100NF
X7R
C9
1UF
X5R
D2
6.2V
C28
100NF
X7R
C32
+
C18
NC
1UF
X5R
D4
6.2V
1
2
R27
1K
R28
1k
R42
1k
+
C51
220UF/25V
1
2
1
2
1
5%
2 1
2
1
5%
2 1
2
1
2
C7
1UF
X7R
R8
10
C17
390PF
NPO
C29
1UF
X7R
1
2
1
2
+
+
R22
10
C36
390PF
NPO
R40
10K
5%
R41
10K
5%
1K
1K
C4
100UF/25V
1
5%
2
C25
R24
3K
5%
100UF/25V
5%
5%
1
5%
2
R9
10K
R23
10K
L5
D1
MBRS130LTR
D3
MBRS130LTR
5%
1
2
L6
10uH
10uH
R25
10K
1
2
1
2
C11
470NF
C33
470NF
FILM
MUTEC
C37
1UF
X5R
1
5%
2
1
5%
2
FILM
C38
+
1000UF/25V
R6
10
C16
100NF
X7R
1000UF/25V
R20
10
C35
100NF
X7R
C39
1K
5%
+
1
2
3
4
5
6
7
8
2
1
TUNER1 IN
2
1
TUNER1
ADDRESS
TUNER
IF
+24V
1 2
+24V
D
FQ1236 / : NTSC TV
TH1
GND1
TH2
GND2
NC
NC
VS_TUNER
SCL
SDA
AS
NC
NC
AF-R
AF-L
2nd SIF OUT
C2 86
CVBS
VS_IF
AF /MPX
GND3
GND4
TH3
TH4
AV , TUNER I/O
1 2
1R21 20
TU_VCC
TU_12V
1
2
3
4
5
6
7
8
9
10
11
12
J11
ROUT
1
2
LOUT
3
4
VIDEO OUT
5
6
7
CON7
2 R47
1 2
21
R66 21
R67
1
R12
1 2
3
2
+
-
AGND
OUT
1 R15 47K 2
1
1 2 2
1
1 2
2
1 2
1
1
2
3
4
100K 5%
PIN PGND
NIN SW
AGND VPP
EN
BS
8
7
6
5
1 2
1 2
1 2
1 2
1 2
LOUT
D
GNDS
GNDS
GNDS
GNDS
1R41 20
GNDS
D13
TU_12V
1N4001
D12
9V
1N4001
J3
1
2
3
4
5
6
CON6
2 1
2
1
1 2
+24V
C
TUNER1 SIF1 BPF
NTSC 4.5MHz PAL 6MHz
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SIF_12V
1Q3
2N3904
1 2
VCC
BL1
1 2
1
2
3
4
1
2
3
4
D11 SR240 +24V
1 2
1 2
VIDEO OUT
LMUTE
PMUTE
AGND
AUSPL
AUSPR
J5
1
2
3
4
5
6
CON6
EXTR
PGND
EXTL
PGND
J2
1
2
3
4
5
CON5
1 2
2 R33
21
R45
21
R46
5
R39
1 1 2 6
+
-
AGND
OUT
1 2
7
1 2 2
LOUT
ROUT
K1
1
EXTL
INTL
EXTR
INTR
1 2
2
1 2 1
2
3
4
1
100K 5%
PIN PGND
NIN SW
AGND VPP
EN
BS
8
7
6
5
1 2
1 2
1 2
1 2
1 2
ROUT
C
GND V
GND V
GND V
GND V
GND V
1 2
GND V GND V GND V
INTL
J7
1
2
3
CON3
INTR
1
2
1
2
9V
C58
100n
C62
330U/16V
Q9
7805
C63
100U/16V
TU_VCC
C61
100n
+24V
G6A-234P
D10
1N4148
R31
PMUTE 1 2
Q8
2N3904
INT: 0
EXT: 1
1 2
1 2 1 2
+24V
B
1 2
1 2
1 2
1 2
SCL
SDA
TU_VCC
1 2
VCC
GNDS
GNDS
2
1 1 2 1 2 1 2 1 2
1 2
1 2
1 2
3
2
+
1 C49 2 AGND
-
OUT
1
1 2
+24V
2 R13
1
1 2
AGND
LOUT
ROUT
+24V
D6
1N4148
Q1
2N3906
2
2
1
1
Q2
2N3904
1 2
Q3
2 R29
2N3904
1 MUTE
B
TU_12V
GNDS
1 2
SIF_12V
GND V
2
1 1 2 1 2 1 2 1 2
1 2
1 2
5
6
+
1 C50 2 AGND
-
OUT
7
2 R26
1
1 2
AGND
AGND
D8
1N4148
D5
Q4
1015
AGND
AGND
LOUT
MUTEB
2 R34
Q5
1
2N3904
AGND
AGND
A
1 2
1R14 1 0 2
1R15 1 0 2
1R16 1 0/NC 2
AF1_OUT
SIF1_OUT
TU_12V
TU_VCC
GND V
AUDIO GROUND
GNDS
VIDEO GROUND
9
8
7
6
2
9
2
3
8
3
4
7
4
5
6
5
NC
GNDS
9
8
7
6
2
9
2
3
8
3
4
7
4
5
6
5
NC
GNDS
9
8
7
6
9
8
7
6
NC
2
2
3
3
4
4
5
5
9
8
7
6
9
8
7
6
NC
2
2
3
3
4
4
5
5
1 2
NC
D9
1N4148
LMUTE
AGND
AGND
Q7
1015
R35 1 2
AGND
Q6
2N3904
ROUT
A
AGND
Title
Size Number
Revision
D
Date: 21-Sep-2005 Sheet of
File: D:\ 正 在 进 行 的 项 目 \LCD TV\LCD TV.DdbDrawn By:

A
B
C
D
E
MT5351RA-V2
MT5111 / MT5351 REFERENCE DESIGN - 4 LAYERS
Rev
AO1MCLK
VOB0
5 AO1MCLK
AO1LRCK
NAME
TYPE
DEVICE
7 RN3 8
VOB1
5 AO1LRCK
5 6
AO1BCK
VOB2
5 AO1BCK
3 4
AO1SDATA0
VOB3
5 AO1SDATA0
+12V
POWER +12V POWER SUPPLY
1 2
33x4 RN0603/SMD
ASPDIF
VOB4
5 ASPDIF
+5V
POWER +5V
POWER SUPPLY
7 RN4 8
VOB5
5 6
DIGITAL AUDIO INTERFACE
VOB6
3 4
VOB7
+5V_tuner POWER +5V
TUNER POWER
1
33x4
2
RN0603/SMD
VOG0
7 RN5 8
DV33_DM POWER +3V3 MT5111 POWER
VOG1
5 6
AUD_CTRL
VOG2
5 AUD_CTRL
3 4
DV18
POWER +1V8 MT5111 POWER
VOG3
1 2
24
33x4 RN0603/SMD
DV33
POWER +3V3 MT5351 POWER
25
VOG4
7 RN6 8
26
AV33
POWER +3V3 MT5351 ANALOG POWER
VOG5
5 6
27
VOG6
3 4
28
DV25
POWER +2V5 MT5351 DDR POWER
VOG7
1 2
29
2 2
33x4 RN0603/SMD
30
DV12
POWER +1V2 MT5351 POWER
VOR0
7 RN7 8
31
VOR1
5 6
32
VOR2
3 4
33
VOR3
1 2
34
33x4 RN0603/SMD
35
VOR4
7 RN8 8
36
VOR5
GND GROUND GROUND
5 6
37
VOR6
3 4
38
VOR7
1 2
39
33x4 RN0603/SMD
40
VOHSYNC 7 RN9 8
41
VOVSYNC 5 6
42
VODE
3 4
43
R4
6
VOPCLK 1 2
ASPDIF
6
44
3
33x4 RN0603/SMD
33
IN
45
2
ORESET# 7 RN10
VCC
8
46
1
READY#
G
5 6
47
7
REQUEST#
G
3 4
48
1 2
49
33x4 RN0603/SMD
50
+5V
History
P#
DATE
RA-V1 INITIAL VERSION 2005/06/15
L19 FB
6
+5V
RA-V2 ADDED AUDIO SWITCH / REFINE POWER CIRCUIT 2005/07/14
7
L2 FB
+12V
2 +12V
8
BEAD/SMD/1206
+5V
2,6 +5V
DV33
8x1 W/HOUSING
220uF/16v
2,5,6,8 DV33
4 4
DIP8/W/H/P2.54
C220UF16V/D6H11
GND
U1
03. TUNER
AUD_CTRL 1
ASPDIF
S
YA 5 ASPDIF
04. MT5111 ASIC
15
OE YB 7
AO1SDATA0
YC 9
2
AO1LRCK
IA0 YD
U0RX
05. MT5351 ASIC
5
AO1BCK
IB0
DV33
5,8 U0RX
11
U0TX
AO1MCLK
IC0
5,8 U0TX
14
U2TX
06. MT5351 PERIPHERAL
ID0 VCC 16
5,8 U2TX
U2RX
5,8 U2RX
3
CB1
IA1
07. DDR MEMORY
6
0.1uF
IB1
UART (RS232)
10
C0603/SMD
IC1
13
08. NOR FLASH / JTAG / UART
ID1 GND 8
+ CE2
2,3,4,5,6,7,8 GND
+3.3V
ORESET#
4,5,8 ORESET#
REQUEST#
5 REQUEST#
POWER INPUT FROM MAIN BOARD
READY#
5 READY#
01. INDEX AND INTERFACE
NS : NON-STUFF
DV33
GLOBAL SIGNAL
R1
4.7K
02. POWER
R0603/SMD
3 3
NC/IDTQS3VH257
VOR[0..7]
TSSOP16/P0.65/SMD
HA1
5 VOR[0..7]
VOG[0..7]
5 VOG[0..7]
VOB[0..7]
U0TX
5 VOB[0..7]
7 RN1 8
1
VOPCLK
U0RX
5 VOPCLK
5 6
2
VOHSYNC
U2RX
5,8 VOHSYNC
3 4
3
VOVSYNC
U2TX
5,8 VOVSYNC
VODE
5 VODE
1
33x4
2
RN0603/SMD
4
5
AO1MCLK R2 75
6
AO1BCK R3 75
7
DIGITAL VIDEO OUTPUT
AO1LRCK R49 75
8
AO1SDATA0 R50 75
9
R0603/SMD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
K1
K2
8
9
4
8
5
9
P1
S/PDIF OUT
RCA/SPDIF/5P/DIP
J1
1
2
3
4
5
+12V
+ CE1
220uF/16v
C220UF16V/D6H11
FB1
HEADER 50 SMD0.5 BOTTOM
H50S/P0.5
FB
1 BEAD/SMD/0603 CB2
1
0.1uF
C0603/SMD
DIGITAL OUTPUT
BEAD/SMD/1206
L1 FB
BOTTOM
CB142
0.1uF
C0603/SMD
SPDIF CIRCUIT
Title POWER
Size Document Number Rev
A
B
C
D
Date: Sheet of
E

A
1
1
1
2
1
1
1
B
C
D
E
FB
L17
BEAD/SMD/0805/NC
9V
+5V U2
DV33
L3
3
IN OUT
2
+12V
FB
U3
L4 +5V_TUNER
+ CE3
CB3
R5 BEAD/SMD/0805 + CE4
CB4
3
220uF/16v
AZ1117/adj 110
+12V
IN OUT
2
0.1uF
220uF/16v
0.1uF
FB
C220UF16V/D6H11 C0603/SMD
SOT223/SMD R0603/SMD
C220UF16V/D6H11 C0603/SMD
1 +12V
+5V
BEAD/SMD/0805
1,6 +5V
DV33
1,5,6,8 DV33
4 CB5
VOUT
4
+ CE5
+ CE6
CB6
4
220uF/16v
0.1uF
220uF/16v
0.1uF
+5V_TUNER
C220UF16V/D6H11 C0603/SMD
C220UF16V/D6H11 C0603/SMD
3,4 +5V_TUNER
DV33_DM
AP1084/TO220-DIP/5V
R6
4 DV33_DM
DV18
TO220/DIP
180
4 DV18
1.25 x (1+180/110) = 3.3V
R0603/SMD
AV33
5,6 AV33
DV25
5,6,7 DV25
DV12
5,6 DV12
ADJ
POWER SUPPLY +5V FOR TUNER
L18
U4
BEAD/SMD/0805/nc
+5V DV33_DM
FB
L5
3
IN OUT
2
FB
+ CE7
CB7
R7 BEAD/SMD/0805 + CE8
CB8
220uF/16v
0.1uF
AZ1117/adj 110
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
SOT223/SMD R0603/SMD
C220UF16V/D6H11 C0603/SMD
ADJ/GND
ADJ/GND
DV33
+ CE9
220uF/16v
C220UF16V/D6H11
POWER SUPPLY +3V3 FOR MT5351
L6
FB
CB9 BEAD/SMD/0805
0.1uF
C0603/SMD
AV33
+ CE10
220uF/16v
C220UF16V/D6H11
CB10
0.1uF
C0603/SMD
1,3,4,5,6,7,8
GND
GLOBAL SIGNAL
GND
R8
180 1.25 x (1+180/110) = 3.3V
R0603/SMD
POWER SUPPLY +3V3 FOR MT5111
POWER SUPPLY +3V3 FOR MT5351 (ANALOG)
DV33_DM
3 U5
DV18
+5V U6
DV25
3
L7
L8
3
IN OUT
2
3
IN OUT
2
FB
FB
R9 BEAD/SMD/0805 + CE12
CB12
+ CE13
CB13
R10 BEAD/SMD/0805 + CE14
CB14
AZ1117/adj 270
220uF/16v
0.1uF
220uF/16v
0.1uF
AZ1117/adj 100
220uF/16v
0.1uF
SOT223/SMD R0603/SMD
C220UF16V/D6H11 C0603/SMD
C220UF16V/D6H11 C0603/SMD
SOT223/SMD R0603/SMD
C220UF16V/D6H11 C0603/SMD
ADJ/GND
ADJ/GND
R11
120 1.25 x (1+120/270) = 1.8V
R0603/SMD
POWER SUPPLY +1V8 FOR MT5111
R12
100 1.25 x (1+100/100) = 2.5V
R0603/SMD
POWER SUPPLY +2V5 FOR MT5351 AND DDR
+5V
+ CE30
470uF/16v/NC
C220UF16V/D6H11
L32
FB
CB146 BEAD/SMD/1206/NC+ CE31
0.1uF/NC
470uF/16v/NC
C0603/SMD
C220UF16V/D6H11
+5V_TUNER
CB147
0.1uF/NC
C0603/SMD
DV33
+ CE15
220uF/16v
C220UF16V/D6H11
3
CB15
0.1uF
C0603/SMD
U7
IN
ADJ/GND
OUT
2
AZ1117/adj
SOT223/SMD
L9
FB
R13 BEAD/SMD/0805
100
R0603/SMD
DV12
+ CE16
220uF/16v
C220UF16V/D6H11
CB16
0.1uF
C0603/SMD
R14
2 0
2
1.25 x (1+0/100) = 1.25V
R0603/SMD
ADD
POWER SUPPLY +1V2 FOR MT5351
L33
4.7UH
DV25
+5V
CB151
10uF
C0805/SMD
4
1
U21 MP2105
IN SW 3
EN FB
5
GND
FB
R112
499k
R0603/SMD
R113
249k
R0603/SMD
CB150
10uF
C0805/SMD
Compatible With U6
1 1
Title
POWER
Size Document Number Rev
Custom MT5351RA-V2 1
A
B
C
D
Monday, September 26, 2005
Date: Sheet of 2 8
E
TwinSon Chan

A
B
C
D
E
U8
L10
+5V_TUNER
FB
GND
TH1
4 + CE17 BEAD/SMD/0805
+5V_TUNER
GND
TH2
CB17
4
0.1uF
10uF/16v
C0603/SMD C10UF16V/D5H11
Outdoor PS 1
VS_splitter_+5V 2
OOB_OP 3
NC 4
RF_AGC 5
NC 6
AS 7
SCL
8
SDA 9
NC 10
VS_Tuner_+5V 11
Broad_IF_OP 12
IF_AGC 13
Narrow_IF_OP1
14
Narrow_IF_OP2
15
GND
TH3
GND
TH4
R17 NS R0603/SMD
R18 100 R0603/SMD
R19 100 R0603/SMD
L11
+5V_TUNER
FB
CB18 + CE18 BEAD/SMD/0805
0.1uF
C0603/SMD
10uF/16v
C10UF16V/D5H11
R15
10K
R0603/SMD
R16
10K
R0603/SMD
TUNER_SCLO
TUNER_SDAO
R20
IF_AGC
4.7K
PORT TUNER TD1336/FGHP
C3 R0603/SMD
10nF
C0603/SMD
3 3
2,4 +5V_TUNER
+5V_TUNER
+5V_TUNER
1,2,4,5,6,7,8 GND
GND
R22
510/1%
R0603/SMD
C4
1nF
C0603/SMD
C5
0.1uF
C0603/SMD
GLOBAL SIGNAL
R21
510/1%
R0603/SMD
4 2nd_IF+
4 2nd_IF-
U9
1
IN+ OUT+
5
2
IN- OUT-
4
C6
1uF
C0603/SMD
IF SAW FILTER AND AMPLIFIER
ROUTE SYMMETRICALLY
U10
1
VCC_+5V GND 8
2
IN_1 OUT_1
7
RF_AGC
2nd_IF+
4 RF_AGC
4 IF_AGC
4 TUNER_SCLO
4 TUNER_SDAO
3
L12
3
NS
IN_2 OUT_2
6
GND
4
L/IND/SMD/0805
VAGC GND 5
PORT SAW FILTER X6965D SIP5K
C7
upc3218
SIP5K/DIP
1uF
TSSOP8/SMD
2 C0603/SMD
2
C8
10nF
C0603/SMD
R23
4.7K
R0603/SMD
TUNER INTERFACE
RF_AGC
IF_AGC
2nd_IF-
2nd_IF+
2nd_IF-
TUNER_SCLO
TUNER_SDAO
1 1
Title
TUNER
Size Document Number Rev
Custom MT5351RA-V2 1
A
B
C
D
Date: Monday, September 26, 2005
Sheet 3 of 8
E
TwinSon Chan

A
1
2
3
4
5
6
7
8
9
1
7
2
2
7
7
7
B
C
D
E
2,3 +5V_TUNER
2 DV33_DM
2 DV18
1,2,3,5,6,7,8 GND
+5V_TUNER
DV33_DM
DV18
GND
DVDD33
1,5,8
ORESET#
ORESET#
DVDD18
MT5111_RF_AGC
MT5111_IF_AGC
AVDD33
DVDD33
TUNER_SCL
TUNER_SDA
R27 4.7K R0603/SMD
R25 4.7K R0603/SMD/NC
AVDD33
DVDD18
DVDD33
DVDD33
DVDD18
DVDD18
DVDD33
10
11
AVDD5 12
13
14
15
16
17
18
19
20
21
22
23
24
25
ADVDD33_2
TS1DATA7_T
TS1DATA6
TS1DATA5
TS1DATA4
TS1SYNC
TS1CLK
DV33_DM
CB148
0.1uF
C0603/SMD
TS1CLK#
12
11
D
CLK
PR 10
CL
13
U12B
VCC 14
Q 9
Q 8
GND 7
74HC74
SOP14/SMD
GLOBAL SIGNAL
MT5111_RF_AGC R24
RF_AGC
RF_AGC
1K
C9
3 RF_AGC
IF_AGC
4 R0603/SMD 47nF
3 IF_AGC
4
C0603/SMD
2nd_IF+
3 2nd_IF+
2nd_IF-
3 2nd_IF-
MT5111_IF_AGC R26
IF_AGC
TUNER_SCLO
1K
C10
3 TUNER_SCLO
TUNER_SDAO
R0603/SMD 47nF
3 TUNER_SDAO
C0603/SMD
TUNER INTERFACE
U11
Close to MT5111
MT5111AE
TS1DATA[0..7]
5 TS1DATA[0..7]
TS1SYNC
5 TS1SYNC
TS1VALID
2nd_IF- C11
ADVDD33_1
5 TS1VALID
76
TS1ERROR
1uF
ADVDD33
NC 50
5 TS1ERROR
77
TS1CLK
C0603/SMD
NC
NC 49
ORESET#
5 TS1CLK
78
L13
NC
RESET_
48
C12
79
OSCL_MST
TS INPUT
NS/220nH NS/47pF
AVDD33
AVSS
HOST_CLK 47
80
L/IND/SMD/0805 C0603/SMD
AVDD
DGND 46
81
DVDD18
2nd_IF+ C13
IN-
DVDD18
45
82
OSDA_MST
1uF
AVDD33
IN+
HOST_DATA 44
83
OSDA_MST
C0603/SMD
C14 0.1uF
AVDD
DGND33
43
DVDD33
6 OSDA_MST
84
OSCL_MST
C0603/SMD
NC
DVDD33
42
6 OSCL_MST
85
C15 0.1uF
REFBOT
AVSS
DGND 41
86
DVDD18
C0603/SMD C16
VCMEXT
REFBOT
DVDD18
40
87
1 RN11 2 TS1ERROR
10uF/10v
VCMEXT
TS_ERR 39
88
3 4 TS1VALID
C17 0.1uF
C0805/SMD
REFTOP
REFTOP
TS_VAL
38
89
5 6 TS1CLK
C0603/SMD
AVSS
TS_CLK 37
90
7 8 TS1SYNC
AVDD33
AVDD18
DGND 36
91
DVDD33
33x4
DVDD18 FB2
AVDD3
AVDD
DVDD33
35
92
RN0603/SMD
AVDD33
AVDD
TS_SYNC 34
93
FB
C18
AVDD
TS_DATA0
33
94
1 RN12 2 TS1DATA0
BEAD/SMD/0603 0.1uF
AVSS
TS_DATA1
32
95
3 4 TS1DATA1
C0603/SMD XTAL2
AVSS
DGND 31
96
DVDD18
5 6 TS1DATA2
XTAL1
XTAL2
DVDD18
30
97
7 8 TS1DATA3
XTAL1
TS_DATA2
29
3 98
33x4
3
AVDD33
AVSS
TS_DATA3
28
C19
99
RN0603/SMD
Y1
18pF
AVDD
DGND 27
100
DVDD33
AVSS
DVDD33
26
25MHz R28
C0603/SMD
CRYS/DIP/SMD 1M
C20
R0603/SMD 18pF
C0603/SMD
DVDD18
75
DGND 74
RF_AGC 73
IF_AGC 72
DGND 71
DVDD33
70
TUNER_CLK 69
TUNER_DATA 68
SA1
67
SA0
66
DGND 65
DVDD18
64
DGND 63
ANTIF
62
DGND 61
DVDD33
60
NC 59
NC 58
MT5111AE
100-LQFP
NC 57
DGND 56
DVDD18
55
NC 54
NC 53
DVDD33
52
DGND 51
NC
NC
AVDD
NC
NC
NC
AVSS
NC
NC
AVDD
AVSS
AVDD
NC
NC
ADVDD33
DGND
DVDD33
DVDD18
DGND
NC
NC
TS_DATA7
TS_DATA6
TS_DATA5
TS_DATA4
1 2
3 4
5 6
7 8
RN13
33x4
RN0603/SMD
2
3
D
CLK
PR 4
CL
U12A
VCC 14
Q 5
Q 6
GND 7
74HC74
SOP14/SMD
MODIFIED IN V3
TS1DATA7_T
R111 TS1DATA7
NS/0
R0603/SMD
U20A
U20B
U20C
U20D
1
4
9
12
2 2
3 TS1CLK#
6
8
11 TS1DATA7
TS1CLK
2
TS1DATA7_T 5
TS1ERROR 10
13
14
DV33_DM
CB149
0.1uF
C0603/SMD
14
14
14
74HC00
SOP14/SMD
74HC00
SOP14/SMD
74HC00
SOP14/SMD
74HC00
SOP14/SMD
DV18
L14
FB
BEAD/SMD/0805
+ CE19
10uF/16v
C10UF16V/D5H11
DVDD18
CB22
0.1uF
C0603/SMD
DVDD18
CB19
0.1uF
C0603/SMD
CB23
0.1uF
C0603/SMD
CB24
0.1uF
C0603/SMD
CB25
0.1uF
C0603/SMD
CB20
0.1uF
C0603/SMD
CB21
0.1uF
C0603/SMD
AVDD33
FB3
FB
BEAD/SMD/0603
AVDD3
CB26
0.1uF
C0603/SMD
Digital 1.8V Bypass Caps
R29 R30
R31 R32
10K 10K
4.7K 4.7K
AVDD33
AVDD5
R0603/SMD R0603/SMD
R0603/SMD R0603/SMD
FB4
DV33_DM
DVDD33 DVDD33
TUNER_SDA1
3 QF1 1
TUNER_SDA
FB
CB27
L15
BEAD/SMD/0603 0.1uF
2N7002
FB
CB29 CB30 CB31 CB32 CB33 CB83
C0603/SMD
N-MOSFET
BEAD/SMD/0805 + CE20
CB28
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10uF/16v
0.1uF
C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD
C10UF16V/D5H11 C0603/SMD
AVDD33
ADVDD33_1
TUNER_SCL1
3 QF2 1
TUNER_SCL
Digital 3.3V Bypass Caps
FB5
2N7002
1 FB
CB34
N-MOSFET
1
BEAD/SMD/0603 0.1uF
DV33_DM
AVDD33
AVDD33
C0603/SMD
SIF LEVEL SHIFTER
+5V_TUNER
DV33_DM
L16
FB
BEAD/SMD/0805
+ CE21
10uF/16v
C10UF16V/D5H11
CB40
0.1uF
C0603/SMD
CB35
0.1uF
C0603/SMD
CB36
0.1uF
C0603/SMD
CB37
0.1uF
C0603/SMD
CB38
0.1uF
C0603/SMD
Analog 3.3V Bypass Caps
CB39
0.1uF
C0603/SMD
AVDD33
FB6
FB
BEAD/SMD/0603
ADVDD33_2
CB41
0.1uF
C0603/SMD
TUNER_SDA1
TUNER_SCL1
R33
10
R0603/SMD
R34
10
R0603/SMD
TUNER_SDAO
TUNER_SCLO
Title
MT5111 ASIC
A
B
C
D
Size Document Number Rev
MT5351RA-V2
TwinSon Chan
1
C
Monday, September 26, 2005
Date: Sheet of 4 8
E

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
READY#
DV12
POWE#
POCE0#
POOE0#
RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]
RCLK0#
RCS#
RRAS#
RCAS#
RWE#
RCKE
RBA[0..1]
RCLK1
RCLK1#
RCLK0
PDA[0..22]
PDD[0..7]
U2TX
U2RX
U1RX
U1TX
U0RX
U0TX
AO1MCLK
AO1LRCK
AO1BCK
ASPDIF
OSCL0
OSDA0
DV25
DV33
RVREF
OXTALI
OXTALO
DVDDKP
FS
CAPVPLL
RVREF
CAPVGND
AVDDRKP
AVDD_APLL0
AVDD_APLL1
AVDDBGKP
AVDD_DMPLL1
AVDD_VPLL
AVDDYKP
AVDD_DMPLL0
APLLCAP1
APLLCAP0
ATP1
ATP2
OPWM0
REQUEST#
ORESET#
VCXO0
TS1CLK
TS1ERROR
TS1SYNC
TS1VALID
TS1DATA[0..7]
VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VOHSYNC
VOVSYNC
VODE
AO1SDATA0
U2CTS
OIRI
AUD_CTRL
AVDD_VPLL
RA7
RA2
RDQM0
JTDO
VOR7
G
R
TS1DATA0
PDA1
AVDDYKP
RCLK1
RCKE
RRAS#
RCAS#
RDQ13
VOB4
TS1ERROR
PDA18
PDA14
PDA2
RDQM3
RDQ19
RA13
RDQ1
DONE
OIRI
VOPCLK
VOG7
VOB5
U2CTS
VCXO0
OPWM0
TS1DATA3
PDA22
OXTALO
RDQ30
RDQ20
RBA0
RDQ10
RCLK0
VOR0
VOG1
AO1BCK
U1RX
U0TX
OSCL0
TS1DATA7
TS1DATA4
PDA9
AVDD_APLL1
RA6
VOR6
PDA0
AVDDBGKP
RDQM2
RA11
RDQ6
JRTCK
VOB3
ASPDIF
OSDA0
PDD3
TS1DATA1
PDA17
AVDD_APLL0
RDQ18
RA12
RWE#
RDQ0
VOG6
PDD0
TS1DATA2
PDA21
RDQ29
RDQ25
RA5
RDQ9
VODE
VOG0
POCE0#
PDD1
APLLCAP1
TS1DATA6
PDA8
PDA6
PDA5
RDQ26
RDQ23
RDQ16
RA0
RCS#
VOR5
AO1LRCK
U1TX
RA9
RA4
RA1
RDQS1
RDQS0
RDQ5
VOR1
VOB2
AO1SDATA0
PDD2
APLLCAP0
FS
PDA16
GND
RDQ17
RDQ15
JTCK
JTMS
JTDI
VOR2
VOG5
AO1MCLK
U2RX
VCXO1
PDA20
CAPVGND
RDQ28
RDQ24
RDQ8
RDQ3
RCLK0#
JTRST#
VOVSYNC
VOB7
TS1DATA5
PDA7
PDA4
DVDDKP
RA10
RDQ12
VOR4
VOG3
PDD6
TS1VALID
PDA13
AVDD_DMPLL1
OXTALI
ATP1
RCLK1#
RA8
RA3
RDQM1
RDQ7
RDQ4
ORESET#
VOB1
POOE0#
POWE#
PDD7
PDD4
TS1CLK
AVDDRKP
AVDD_DMPLL0
RDQ14
READY#
REQUEST#
VOG4
CAPVPLL
B
PDA19
PDA15
RDQ27
RDQS3
RDQ2
VOHSYNC
VOB6
AUD_CTRL
U2TX
U0RX
TS1SYNC
PDA11
PDA3
ATP2
RDQ31
RDQS2
RDQ21
RBA1
RDQ11
VOR3
VOG2
VOB0
TUNER_SW
PDD5
PDA12
PDA10
RDQ22
R
B
G
DV33
DV25
DV12
DV33
DV12
JTRST#
8
JTDI
8
JTMS
8
JTCK
8
JRTCK
8
JTDO
8
GND
1,2,3,4,6,7,8
DV12
2,6
POCE0#
8
POOE0#
8
POWE#
8
RDQ[0..31]
7
RDQS[0..3]
7
RDQM[0..3]
7
RA[0..13]
7
RCLK0
7
RCLK0#
7
RCS#
7
RRAS#
7
RCAS#
7
RWE#
7
RCKE
7
RBA[0..1]
7
RCLK1
7
RCLK1#
7
PDA[0..22]
8
PDD[0..7]
8
U2TX
1,8
U2RX
1,8
U1RX
8
U1TX
8
U0RX
1,8
U0TX
1,8
READY#
1
AO1MCLK
1
AO1BCK
1
AO1LRCK
1
AO1SDATA0
1
ASPDIF
1
OPWM0
6
OSCL0
6
OSDA0
6
DV25
2,6,7
DV33
1,2,6,8
RVREF
6
OXTALI
6
OXTALO
6
DVDDKP
6
FS
6
CAPVPLL
6
CAPVGND
6
AVDDRKP
2,6
AVDD_APLL0
2,6
AVDD_APLL1
2,6
AVDDBGKP
2,6
AVDD_DMPLL1
2,6
AVDD_VPLL
2,6
AVDDYKP
2,6
AVDD_DMPLL0
2,6
APLLCAP1
6
APLLCAP0
6
ATP1
6
ATP2
6
REQUEST#
1
ORESET#
1,4,8
VCXO0
6
TS1CLK
4
TS1ERROR
4
TS1SYNC
4
TS1VALID
4
TS1DATA[0..7]
4
VOR[0..7]
1
VOG[0..7]
1
VOB[0..7]
1
VOPCLK
1
VOHSYNC
1,8
VOVSYNC
1,8
VODE
1
U2CTS
6
OIRI
6
AUD_CTRL
1
R
8
B
8
G
8
Title
Size Document Number Rev
Date: Sheet of
MT5351RA-V2 1
Custom
5 8
Monday, September 26, 2005
MT5351 ASIC
TwinSon Chan
JTAG PORT
GLOBAL SIGNAL
DDR MEMORY
FLASH INTERFACE
UART (RS232)
AUDIO INTERFACE
ANALOG PART
TEST PURPOSE
TS INPUT
DIGITAL VIDEO OUTPUT
Add by Ada
R36
330
R0603/SMD
TP6
TUNER_SW
TP/SMD/D1.0
C118
0.1uF
C0603/SMD
TP5
IR
TP/SMD/D1.0
TP2
IOB_Y5
TP/SMD/D1.0
MT5351
U14
MT5351
BGA471/SMD
PDCD2#
A14
PDIOIS16#
A15
PDA0
B24
PDA1
A24
PDA2
D23
PDA3
C23
PDA4
B23
PDA5
A23
PDA6
D22
PDA7
C22
PDA8
B22
PDA9
A22
PDA10
D21
PDA11
C21
PDA12
B21
PDA13
A21
PDA14
D20
PDA15
C20
PDA16
B20
PDA17
A20
PDA18
D19
PDA19
C19
PDA20
B19
PDA21
A19
PDA22
D18
PDA23
C18
PDA24
B18
PDA25
A18
PDCE1#
D17
PDCE2#
C17
PDOE#
B17
PDIORD#
A17
PDIOWR#
D16
PDWE#
C16
PDIREQ#
B16
PDRESET
A16
PDWAIT#
D15
PDINPACK#
C15
PDREG#
B15
PDENPOD B14
T0CLK C14
T0SYNC D14
T0VALID A13
T0DATA0
B13
T0DATA1
C13
T0DATA2
D13
T0DATA3
A12
T0DATA4
B12
T0DATA5
C12
T0DATA6
D12
T0DATA7
A11
T1CLK B11
T1SYNC C11
T1VALID D11
T1DATA0
A10
T1DATA1
B10
T1DATA2
C10
T1DATA3
D10
T1DATA4
A9
T1DATA5
B9
T1DATA6
C9
T1DATA7
D9
OPWM0
D8
ORTCVDD D7
ORTCO B8
ORTCI
A8
OPWM1
C8
ORTCVSS C7
FS A6
CIN_Y0
A7
IOR_Y6
B3
IOB_Y5
A3
IOG_Y4
C4
IOX_Y3
B4
IOY_Y2
A4
IOC_Y1
C5
CAPVPLL
D5
APLLCAP1
D4
APLLCAP0
E4
AGND L11
AGND L12
AGND L13
AGND M11
AGND M12
AGND M13
AGND N11
AGND N12
AGND N13
PDD0
A27
PDD1
B26
PDD2
A26
PDD3
C25
PDD4
B25
PDD5
A25
PDD6
D24
PDD7
C24
PDCD1#
A28
CVDD M5
CVDD N5
CVDD U5
CVDD E10
CVDD E19
CVDD M24
CVDD N24
CVDD U24
CVDD AE14
CVDD AE15
IOVDD
P5
IOVDD
R1
IOVDD
R2
IOVDD
R3
IOVDD
R4
IOVDD
R5
IOVDD
T5
IOVDD
E11
IOVDD
E12
IOVDD
E13
IOVDD
E14
IOVDD
E15
IOVDD
E16
IOVDD
E17
IOVDD
E18
IOVDD
P24
IOVDD
R24
IOVDD
R25
IOVDD
R26
IOVDD
R27
IOVDD
R28
IOVDD
T24
POWE#
B27
POCE0#
B28
POOE0#
C26
POCE1#
C27
POOE1#
C28
POCE2#
D25
POOE2#
D26
OSDA0
E1
OSCL0
F4
OSDA1
E3
OSCL1
E2
U0TX
F3
U0RX
F2
U1TX
F1
U1RX
G4
U2TX
G3
U2RX
G2
U2CTS
G1
U2RTS
H4
AO1SDATA3
H3
AO1SDATA2
H2
AO1SDATA1
H1
AO1SDATA0
J4
AO1LRCK
J3
AO1BCK
J2
AO1MCLK
J1
AO2SDATA0
K1
AO2LRCK
K2
AO2BCK
K3
AO2MCLK
K4
ASPDIF
L3
ASPDIF2
L4
VOB0
L2
VOB1
L1
VOB2
M4
VOB3
M3
VOB4
M2
VOB5
M1
VOB6
N4
VOB7
N3
VOG0
N2
VOG1
N1
VOG2
P4
VOG3
P3
VOG4
P2
VOG5
P1
VOG6
T1
VOG7
T2
VOR0
T3
VOR1
T4
VOR2
U1
VOR3
U2
VOR4
U3
VOR5
U4
VOR6
V1
VOR7
V2
VOPCLK
V3
VOHSYNC
V4
VOVSYNC
W1
VODE
W2
JTRST#
W3
JTDI
W4
JTMS
Y1
JTCK
Y2
JRTCK
Y3
JTDO
Y4
GND
L14
GND
L15
GND
L16
GND
L17
GND
L18
GND
M14
GND
M15
GND
M16
GND
M17
GND
M18
GND
N14
GND
N15
GND
N16
GND
N17
GND
N18
GND
P11
GND
P12
GND
P13
GND
P14
GND
P15
GND
P16
GND
P17
GND
P18
GND
R11
GND
R12
GND
R13
GND
R14
GND
R15
GND
R16
GND
R17
GND
R18
PARB#
D27
PARE#
D28
PACE#
E25
PACLE E26
PAALE E27
PAWE#
E28
ELREQ F25
ECLK F26
ECNTL0
F27
ECNTL1
F28
EDATA0
G25
EDATA1
G26
EDATA2
G27
EDATA3
G28
EDATA4
H25
EDATA5
H26
EDATA6
H27
EDATA7
H28
ELPS J25
ELINKON J26
ORESET#
J27
OIRI
J28
OIRO K25
ICS1#
K26
ICS0#
K27
IDA2
K28
IDA0
L25
IDA1
L26
IINTRQ L27
IDMACK#
L28
IIORDY M25
IDIOR#
M26
IDIOW#
M27
IDMARQ M28
IDD15
N25
IDD0
N26
IDD14
N27
IDD1
N28
IDD13
P25
IDD2
P26
IDD12
P27
IDD3
P28
IDD11
T28
IDD4
T27
IDD10
T26
IDD5
T25
IDD9
U28
IDD6
U27
IDD8
U26
IDD7
U25
IRESET#
V28
DDETECT
V27
DCLK V26
DCMD V25
DDATA0
W28
DDATA1
W27
DDATA2
W26
DDATA3
W25
MDETECT
Y28
MCLK Y27
MBS Y26
MDATA0
Y25
MDATA1
AA28
MDATA2
AA27
MDATA3
AA26
STSCLK AA25
STSDOUT
AB28
STSDIN AB27
SPWRSEL
AB26
SDETECT
AB25
SCMDVCC AC28
SRST
AC27
SCLK AC26
SDATA AC25
GND T11
GND T12
GND T13
GND T14
GND T15
GND T16
GND T17
GND T18
GND U11
GND U12
GND U13
GND U14
GND U15
GND U16
GND U17
GND U18
GND V11
GND V12
GND V13
GND V14
GND V15
GND V16
GND V17
GND V18
DVREF2
AE8
DVREF0
AE9
DVREF1
AE20
DVREF3
AE21
RDQ32
AA1
RDQ33
AA2
RDQ34
AA3
RDQ35
AB1
RDQ36
AB2
RDQ37
AB3
RDQ38
AC1
RDQ39
AC2
RDQS4
AC3
RDQM4
AD1
RDQM5
AD2
RDQS5
AD3
RDQ40
AE1
RDQ41
AE2
RDQ42
AE3
RDQ43
AF1
RDQ44
AF2
RDQ45
AF3
RDQ46
AG1
RDQ47
AG2
RCLK0
AH1
RCLK0#
AH2
RDQ0
AH3
RDQ1
AG3
RDQ2
AH4
RDQ3
AG4
RDQ4
AF4
RDQ5
AH5
RDQ6
AG5
RDQ7
AF5
RDQS0
AH6
RDQM0
AG6
RDQM1
AF6
RDQS1
AH7
RDQ8
AG7
RDQ9
AF7
RDQ10
AH8
RDQ11
AG8
RDQ12
AF8
RDQ13
AH9
RDQ14
AG9
RDQ15
AF9
RWE#
AH10
RCAS#
AG10
RRAS#
AF10
RCS#
AH11
RBA0
AG11
RBA1
AF11
RA10
AH12
RA0
AG12
RA1
AF12
RA2
AH13
RA3
AG13
RA4
AF13
RA5
AH14
RA6
AG14
RA7
AF14
RA8
AH15
RA9
AG15
RA11
AF15
RA12
AH16
RA13
AG16
RCKE
AF16
RDQ16
AH17
RDQ17
AG17
RDQ18
AF17
RDQ19
AH18
RDQ20
AG18
RDQ21
AF18
RDQ22
AH19
RDQ23
AG19
RDQS2
AF19
RDQM2
AH20
RDQM3
AG20
RDQS3
AF20
RDQ24
AH21
RDQ25
AG21
RDQ26
AF21
RDQ27
AH22
RDQ28
AG22
RDQ29
AF22
RDQ30
AH23
RDQ31
AG23
RCLK1
AF23
RCLK1#
AH24
RDQ48
AG24
RDQ49
AF24
RDQ50
AH25
RDQ51
AG25
RDQ52
AF25
RDQ53
AH26
RDQ54
AG26
RDQ55
AH27
RDQS6
AH28
RDQM6
AG28
RDQM7
AG27
RDQS7
AF28
RDQ56
AF27
RDQ57
AF26
RDQ58
AE28
RDQ59
AE27
RDQ60
AE26
RDQ61
AD28
RDQ62
AD27
RDQ63
AD26
RVDD
AA4
RVDD
AB4
RVDD
AC4
RVDD
AD4
RVDD
AE4
RVDD
AE5
RVDD
AE6
RVDD
AE7
RVDD
AE10
RVDD
AE11
RVDD
AE12
RVDD
AE13
RVDD
AE16
RVDD
AE17
RVDD
AE18
RVDD
AE19
RVDD
AE22
RVDD
AE23
RVDD
AE24
RVDD
AE25
RVDD
AD25
ATP1
D2
AVDD_APLL0
C2
AVDD_APLL1
B1
AVDD_VPLL
A1
AVDD_DMPLL0
C1
AVDDRKP C3
AVDDYKP B5
AVDDBGKP B6
DACVREF
B7
DVDDKP C6
OXTALO A2
OXTALI
B2
NC A5
NC D6
AVDD_DMPLL1
D3
ATP2
D1
CAPVGND E5
+ CE22
47uF/16v
C10UF16V/D5H11
TP4
VCXO1
TP/SMD/D1.0
TP3
IOG_Y4
TP/SMD/D1.0
R35
4.7K
R0603/SMD
LED1
LED DIP2.54
LED/DIP/P2.54
C116
0.1uF
C0603/SMD
TP1
IOR_Y6
TP/SMD/D1.0
C117
0.1uF
C0603/SMD

5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
RVREF
GND
OXTALI
OXTALO
OPWM0
OXTALO
OXTALI
MEM_VREF
FS
APLLCAP1
APLLCAP0
DV25
DV33
DV12
AVDDBGKP
AVDDYKP
AVDDRKP
AVDD_DMPLL0
AVDD_DMPLL1
AVDD_VPLL
AVDD_APLL1
AVDD_APLL0
MEM_VREF
RVREF
CAPVPLL
AV33
DVDDKP
FS
CAPVPLL
APLLCAP1
APLLCAP0
ATP1
ATP2
AVDDRKP
AVDD_APLL0
AVDD_APLL1
AVDDBGKP
AVDD_DMPLL1
AVDD_VPLL
AVDDYKP
AVDD_DMPLL0
CAPVGND
ATP1
ATP2
OSCL_MST
OSDA_MST
OSDA0
OSCL0
OSCL_MST
OSDA_MST
OPWM0
OSCL_MST
OSDA_MST
OSCL0
OSDA0
VCXO0
VCXO0
CAPVGND
OXTALI
U2CTS
U2CTS
OIRI
OIRI
+5V
DV25
DV12
DV33
DV33
DVDDKP
AV33
AV33
AV33
DV12
DV33
DV33
DV33
+5V
GND
1,2,3,4,5,7,8
DV25
2,5,7
RVREF
5
OXTALI
5
OXTALO
5
OPWM0
5
MEM_VREF
7
DV33
1,2,5,8
DV12
2,5
AV33
2,5
DVDDKP
5
FS
5
CAPVPLL
5
APLLCAP1
5
APLLCAP0
5
ATP1
5
ATP2
5
AVDDRKP
2,5
AVDD_APLL0
2,5
AVDD_APLL1
2,5
AVDDBGKP
2,5
AVDD_DMPLL1
2,5
AVDD_VPLL
2,5
AVDDYKP
2,5
AVDD_DMPLL0
2,5
CAPVGND
5
OSDA_MST
4
OSCL_MST
4
OSCL0
5
OSDA0
5
VCXO0
5
U2CTS
5
OIRI
5
+5V
1,2
Title
Size Document Number Rev
Date: Sheet of
MT5351RA-V2 1
Custom
6 8
Monday, September 26, 2005
MT5351 PERIPHERAL
TwinSon Chan
GLOBAL SIGNAL
LEFT SIDE
BOTTOM SIDE
LEFT SIDE
RIGHT SIDE
LEFT SIDE RIGHT SIDE TOP SIDE
TOP SIDE
BOTTOM SIDE
ANALOG PART
MT5351 SYSTEM EEPROM
CB76
0.1uF
C0603/SMD
R45
4.7K
R0603/SMD
CB88
0.1uF
C0603/SMD
C140
0.1uF
C0603/SMD
C22
NS/20pF
C0603/SMD
C31
10uF/10v
C0805/SMD
C183
0.1uF
C0603/SMD
C185
0.1uF
C0603/SMD
CB44
4.7uF
C0603/SMD
CB50
4.7uF
C0603/SMD
CB72
0.1uF
C0603/SMD
R44
NS/10
R0603/SMD
CB75
0.1uF
C0603/SMD
C29
10uF/10v
C0805/SMD
C104
0.1uF
C0603/SMD
X1
VCXO FR270003
OSC/6P/SMD/7X5
CVIN
1
TRI-STATE
2
GND
3
OUT
4
NC 5
VDD 6
C184
0.1uF
C0603/SMD
JP1
JP2/DIP/P2.54
2x1
1 2
R38
NS/10M
R0603/SMD
C128
0.1uF
C0603/SMD
CB67
0.1uF
C0603/SMD
CB57
4.7uF
C0603/SMD
R40
NS/50
R0603/SMD
CB71
0.1uF
C0603/SMD
R39
NS/10
R0603/SMD
C25
1500pF
C0603/SMD
IR1
IR
NS/IR
1
2
3
CB74
0.1uF
C0603/SMD
R43
10
R0603/SMD
C129
0.1uF
C0603/SMD
R47
100
R0603/SMD
OSC1
NS/74.25MHz
OSC/SMD/A
VCC
4
OUT
3
GND 2
NC
1
FB7
FB
BEAD/SMD/0603
CB66
0.1uF
C0603/SMD
CB77
0.1uF
C0603/SMD
CB85
0.1uF
C0603/SMD
R46
4.7K
R0603/SMD
CB90
0.1uF
C0603/SMD
CB87
0.1uF
C0603/SMD
CB70
0.1uF
C0603/SMD
R41
NS/50
R0603/SMD
Y2
NS/27MHz
CRYS/DIP/SMD
CB53
0.1uF
C0603/SMD
C101
10uF/10v
C0805/SMD
C138
4.7uF
C0603/SMD
C26
10nF
C0603/SMD
CB48
0.1uF
C0603/SMD
CB52
0.1uF
C0603/SMD
U13
EEPROM 24C16
SOP8/SMD/NC
NC
1
NC
2
NC
3
GND
4
SDA 5
SCL
6
WP
7
VCC 8
R48
100
R0603/SMD
R42
8.2K
R0603/SMD
R37
NS/560
R0603/SMD
C28
47pF
C0603/SMD
CB54
0.1uF
C0603/SMD
CB69
0.1uF
C0603/SMD
CB81
0.1uF
C0603/SMD
CB89
0.1uF
C0603/SMD
C24
1500pF
C0603/SMD
CB45
0.1uF
C0603/SMD
C186
0.1uF
C0603/SMD
CB42
0.1uF
C0603/SMD
TP7
CAPVGND
TP/SMD/D1.0
CB78
4.7uF
C0603/SMD
CB82
0.1uF
C0603/SMD
CB51
0.1uF
C0603/SMD
CB79
0.1uF
C0603/SMD
CB65
0.1uF
C0603/SMD
CB68
0.1uF
C0603/SMD
C27
1nF
C0603/SMD
C179
0.1uF
C0603/SMD
CB49
0.1uF
C0603/SMD
CB86
0.1uF
C0603/SMD
C21
NS/20pF
C0603/SMD
CB46
0.1uF
C0603/SMD
CB47
4.7uF
C0603/SMD
CB73
0.1uF
C0603/SMD
CB43
0.1uF
C0603/SMD
CB80
0.1uF
C0603/SMD
C23
5600pF
C0603/SMD
L31
FB
L0603/SMD

5
4
3
2
1
+1V25_DDR
+1V25_DDR
D
RWE# 7 RN14 8 22x4 MEM_WE#
RCAS# 5 6 MEM_CAS#
RCS# 3 4 MEM_CS#
RBA0 1 2 MEM_BA0
RA10 7 RN18 8 22x4 MEM_ADDR10
RA0 5 6 MEM_ADDR0
RA2 3 4 MEM_ADDR2
RA3 1 2 MEM_ADDR3
RA5 7 RN22 8 22x4 MEM_ADDR5
RA6 5 6 MEM_ADDR6
RA8 3 4 MEM_ADDR8
RA9 1 2 MEM_ADDR9
RA12 R63 22 MEM_ADDR12
RA13 R65 22 MEM_ADDR13
RRAS# 1 RN30 2 22x4 MEM_RAS#
RBA1 3 4 MEM_BA1
RA1 5 6 MEM_ADDR1
RA4 7 8 MEM_ADDR4
RA7 R67 22 MEM_ADDR7
RA11 R71 22 MEM_ADDR11
RCKE R77 22 MEM_CLKEN
CLOSED TO MT5351
MEM_ADDR5 7 RN15 8 75x4
MEM_ADDR4 5 6
MEM_ADDR13 3 4
MEM_WE# 1 2
MEM_ADDR10 7 RN19 8 75x4
MEM_ADDR0 5 6
MEM_ADDR1 3 4
MEM_ADDR2 1 2
MEM_ADDR9 7 RN23 8 75x4
MEM_ADDR8 5 6
MEM_ADDR7 3 4
MEM_ADDR6 1 2
MEM_ADDR12 R64 75
MEM_CAS# R66 75
MEM_BA1 1 RN31 2 75x4
MEM_BA0 3 4
MEM_CS# 5 6
MEM_RAS# 7 8
MEM_ADDR3 R68 75
MEM_ADDR11 R72 75
MEM_CLKEN R78 NS/75
CLOSED TO DDR
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQS0
RDQM0
RDQM1
RDQS1
RDQ8
RDQ9
RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15
RDQ16
RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23
RDQS2
RDQM2
RDQM3
RDQS3
RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31
7 RN16 8 47x4 MEM_DQ0
5 6 MEM_DQ1
3 4 MEM_DQ2
1 2 MEM_DQ3
7 RN20 8 47x4 MEM_DQ4
5 6 MEM_DQ5
3 4 MEM_DQ6
1 2 MEM_DQ7
R55 47 MEM_DQS0
R57 47 MEM_DQM0
R59 47 MEM_DQM1
R61 47 MEM_DQS1
7 RN24 8 47x4 MEM_DQ8
5 6 MEM_DQ9
3 4 MEM_DQ10
1 2 MEM_DQ11
7 RN26 8 47x4 MEM_DQ12
5 6 MEM_DQ13
3 4 MEM_DQ14
1 2 MEM_DQ15
7 RN28 8 47x4 MEM_DQ16
5 6 MEM_DQ17
3 4 MEM_DQ18
1 2 MEM_DQ19
7 RN32 8 47x4 MEM_DQ20
5 6 MEM_DQ21
3 4 MEM_DQ22
1 2 MEM_DQ23
R69 47 MEM_DQS2
R73 47 MEM_DQM2
R75 47 MEM_DQM3
R79 47 MEM_DQS3
7 RN34 8 47x4 MEM_DQ24
5 6 MEM_DQ25
3 4 MEM_DQ26
1 2 MEM_DQ27
7 RN36 8 47x4 MEM_DQ28
5 6 MEM_DQ29
3 4 MEM_DQ30
1 2 MEM_DQ31
7 RN17 8 75x4
5 6
3 4
1 2
7 RN21 8 75x4
5 6
3 4
1 2
R56 75
R58 75
R60 75
R62 75
7 RN25 8 75x4
5 6
3 4
1 2
7 RN27 8 75x4
5 6
3 4
1 2
7 RN29 8 75x4
5 6
3 4
1 2
7 RN33 8 75x4
5 6
3 4
1 2
R70 75
R74 75
R76 75
R80 75
7 RN35 8 75x4
5 6
3 4
1 2
7 RN37 8 75x4
5 6
3 4
1 2
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQS0
MEM_ADDR13
MEM_DQM0
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
DV25 DV25 DV25 DV25
U15
1
VDD
VSS 66
2
DQ0
DQ15
65
3
VDDQ VSSQ 64
4
DQ1
DQ14
63
5
DQ2
DQ13
62
6
VSSQ VDDQ 61
7
DQ3
DQ12
60
8
DQ4
DQ11
59
9
VDDQ VSSQ 58
10
DQ5
DQ10
57
11
DQ6
DQ9
56
12
VSSQ VDDQ 55
13
DQ7
DQ8
54
14
NC
NC 53
15
VDDQ VSSQ 52
16
LDQS UDQS 51
17
NC
NC 50
18
VDD VREF
49
19
NC
VSS 48
20
LDM
UDM 47
21
WE
CLK 46
22
CAS
CLK 45
23
RAS
CKE 44
24
CS
NC 43
25
NC
A12
42
26
BS0
A11
41
27
BS1
A9
40
28
A10/AP
A8
39
29
A0
A7
38
30
A1
A6
37
31
A2
A5
36
32
A3
A4
35
33
VDD
VSS 34
16M x 16 DDR TSOP-66
TSOP_0D65_22D6LX9D7W_66SP
DDR#1
MEM_DQ15
MEM_DQ14
MEM_DQ13
MEM_DQ12
MEM_DQ11
MEM_DQ10
MEM_DQ9
MEM_DQ8
MEM_DQS1
MEM_VREF
MEM_DQM1
MEM_CLKA#
MEM_CLKA
MEM_CLKEN
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQS2
MEM_ADDR13
MEM_DQM2
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
U18
1
VDD
VSS 66
2
DQ0
DQ15
65
3
VDDQ VSSQ 64
4
DQ1
DQ14
63
5
DQ2
DQ13
62
6
VSSQ VDDQ 61
7
DQ3
DQ12
60
8
DQ4
DQ11
59
9
VDDQ VSSQ 58
10
DQ5
DQ10
57
11
DQ6
DQ9
56
12
VSSQ VDDQ 55
13
DQ7
DQ8
54
14
NC
NC 53
15
VDDQ VSSQ 52
16
LDQS UDQS 51
17
NC
NC 50
18
VDD VREF
49
19
NC
VSS 48
20
LDM
UDM 47
21
WE
CLK 46
22
CAS
CLK 45
23
RAS
CKE 44
24
CS
NC 43
25
NC
A12
42
26
BS0
A11
41
27
BS1
A9
40
28
A10/AP
A8
39
29
A0
A7
38
30
A1
A6
37
31
A2
A5
36
32
A3
A4
35
33
VDD
VSS 34
16M x 16 DDR TSOP-66
TSOP_0D65_22D6LX9D7W_66SP
DDR#2
MEM_DQ31
MEM_DQ30
MEM_DQ29
MEM_DQ28
MEM_DQ27
MEM_DQ26
MEM_DQ25
MEM_DQ24
MEM_DQS3
MEM_VREF
MEM_DQM3
MEM_CLKB#
MEM_CLKB
MEM_CLKEN
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
DV25
2,5,6 DV25
GND
1,2,3,4,5,6,8 GND
GLOBAL SIGNAL
RDQ[0..31]
5 RDQ[0..31]
RDQS[0..3]
5 RDQS[0..3]
RDQM[0..3]
5 RDQM[0..3]
RA[0..13]
5 RA[0..13]
RBA[0..1]
5 RBA[0..1]
RCLK0
5 RCLK0
RCLK0#
5 RCLK0#
RCS#
5 RCS#
RRAS#
5 RRAS#
RCAS#
5 RCAS#
RWE#
5 RWE#
RCKE
5 RCKE
RCLK1
5 RCLK1
RCLK1#
5 RCLK1#
MEM_VREF
6 MEM_VREF
DDR MEMORY
EQUAL LINE LENGTH
D
RCLK0
R102
47
R0603/SMD
MEM_CLKA
R103
100
R0603/SMD
CLOSED TO MT5351
CLOSED TO DDR
RCLK0#
R105
47
R0603/SMD
MEM_CLKA#
C
C
RCLK1
R106
47
R0603/SMD
MEM_CLKB
R107
100
R0603/SMD
RCLK1#
R108
47
R0603/SMD
MEM_CLKB#
+1V25_DDR
CLOSED TO MT5351
CLOSED TO DDR
CB91
0.1uF
C0603/SMD
+ CE23
220uF/16v
C220UF16V/D6H11
R104
4.7K
R0603/SMD
+1V25_DDR
C168
0.1uF
C0603/SMD
+1V25_DDR
C146
0.1uF
C0603/SMD
C169
0.1uF
C0603/SMD
C147
0.1uF
C0603/SMD
CB95
0.1uF
C0603/SMD
C148
0.1uF
C0603/SMD
C171
0.1uF
C0603/SMD
C150
0.1uF
C0603/SMD
C170
0.1uF
C0603/SMD
C151
0.1uF
C0603/SMD
C180
0.1uF
C0603/SMD
C160
0.1uF
C0603/SMD
C181
0.1uF
C0603/SMD
C161
0.1uF
C0603/SMD
C141
0.1uF
C0603/SMD
C162
0.1uF
C0603/SMD
C142
0.1uF
C0603/SMD
C163
0.1uF
C0603/SMD
C143
0.1uF
C0603/SMD
C164
0.1uF
C0603/SMD
C144
0.1uF
C0603/SMD
C165
0.1uF
C0603/SMD
C145
0.1uF
C0603/SMD
C166
0.1uF
C0603/SMD
DV25
DV25
+ CE25
220uF/16v
C220UF16V/D6H11
C153
0.1uF
C0603/SMD
C154
0.1uF
C0603/SMD
C155
0.1uF
C156
0.1uF
C157
0.1uF
C0603/SMD C0603/SMD C0603/SMD
FOR DDR#1
C158
0.1uF
C0603/SMD
C159
0.1uF
C0603/SMD
C172
0.1uF
C0603/SMD
C152
0.1uF
C0603/SMD
MEM_VREF
C139
0.1uF
C0603/SMD
U19
1
GND VTT
8
2
SD PVIN 7
3
VSENSE AVIN 6
4
VREF VDDQ 5
IC LP2996 DDR Termination SOP-8
SOP8/SMD
DV25
+ CE24
47uF/16v
C47UF16V/D5H5
BYPASS CAP. FOR DIMM
+1V25_DDR FOR DDR TERMINATOR
MEM_VREF FOR DDR AND MT5351 VREF
B
+1V25_DDR
CB133
0.1uF
C0603/SMD
C167
0.1uF
C0603/SMD
BYPASS CAP. FOR TERMINATOR
(EVERY 2 RESISTOR PUT 1 BYPASS CAP.)
+ CE26
220uF/16v
C220UF16V/D6H11
CB125
0.1uF
C0603/SMD
CB126
0.1uF
C0603/SMD
C173
0.1uF
C0603/SMD
C174
0.1uF
C0603/SMD
FOR DDR#2
BYPASS CAP. FOR DDR
C175
0.1uF
C0603/SMD
C176
0.1uF
C0603/SMD
C177
0.1uF
C0603/SMD
C178
0.1uF
C0603/SMD
+1V25_DDR
B
DV25
C102
0.1uF
C0603/SMD
C105
0.1uF
C0603/SMD
C106
0.1uF
C0603/SMD
C107
0.1uF
C0603/SMD
C108
0.1uF
C0603/SMD
C109
0.1uF
C0603/SMD
C110
0.1uF
C0603/SMD
C111
0.1uF
C0603/SMD
C103
0.1uF
C182
0.1uF
C0603/SMD
C0603/SMD
+ CE28
220uF/16v
C220UF16V/D6H11
+ CE29
220uF/16v
C220UF16V/D6H11
ADD by Ada
A
A
Title
DDR MEMORY
5
4
3
2
Size Document Number Rev
TwinSon Chan
MT5351RA-V2 1
Custom
Monday, September 26, 2005
Date: Sheet of 7 8
1

5
4
3
2
1
D
DV33
R87
4.7K
R0603/SMD
ORESET#
C33
10pF
C0603/SMD
R88
0
R0603/SMD
PDA1
PDA2
PDA3
PDA4
PDA5
PDA6
PDA7
PDA8
PDA9
PDA10
PDA11
PDA12
PDA13
PDA14
PDA15
PDA16
PDA17
PDA18
PDA19
PDA20
PDA21
PDA22
POCE0#
POOE0#
POWE#
NOR_RST#
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
10
13
26
28
11
12
U17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
CE
OE
WE
RESET
D0
29
D1
31
D2
33
D3
35
D4
38
D5
40
D6
42
D7
44
D8
30
D9
32
D10
34
D11
36
D12
39
D13
41
D14
43
D15/A-1
45
WP/ACC 14
BYTE 47
VCC 37
GND1
GND2
27
46
NOR FLASH #0
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDA0
IC FLASH MX29LV320 32Mb TSOP-48
TSOP48/SMD
NOR_WP#
NOR_RY_BY0#
R86
NS/4.7K
R0603/SMD
CB145
0.1uF
C0603/SMD
R84
ORESET#
0
R0603/SMD
FB9
C32
NS/10pF
C0603/SMD
DV33
FB
+ CE27
BEAD/SMD/0603
10uF/16v
C10UF16V/D5H11
U0RX
U0TX
DV33
R82
NS/4.7K
R0603/SMD
PDA0
R89
4.7K
R0603/SMD
DV33
R83
NS/4.7K
R0603/SMD
PDA1
TRAP CIRCUIT
R90
4.7K
R0603/SMD
DV33
1
2
3
4
J2
PDA2
R85
NS/4.7K
R0603/SMD
+5V
1,2,6 +5V
DV33
1,2,5,6 DV33
GND
1,2,3,4,5,6,7 GND
ORESET#
1,4,5 ORESET#
GLOBAL SIGNAL
POCE0#
5 POCE0#
POOE0#
5 POOE0#
POWE#
5 POWE#
PDD[0..7]
5 PDD[0..7]
PDA[0..22]
5 PDA[0..22]
FLASH INTERFACE
JTRST#
5 JTRST#
JTDI
5 JTDI
JTMS
5 JTMS
JTCK
5 JTCK
JRTCK
5 JRTCK
JTDO
5 JTDO
JTAG PORT
D
C
JRTCK
JTDO
R91
1K
R0603/SMD
JTRST#
JTDI
JTMS
JTCK
R96 0 R0603/SMD
R97 0 R0603/SMD
1 2
3 4
5 6
7 8
DV33
RN38
1Kx4
RN0603/SMD
R92
4.7K
R0603/SMD
R93
4.7K
R0603/SMD
TVTREF#1
JTAG_DBGRQ
JTAG_DBGACK
1
3
5
7
9
11
13
15
17
19
J3
2
4
6
8
10
12
14
16
18
20
CLI OUTPUT
U1RX
U1TX
R94
4.7K
R0603/SMD
R95
4.7K
R0603/SMD
DV33
SOFTWARE DEBUG PORT
1
2
3
4
4x1 W/HOUSING
DIP4/W/H/P2.0
J4
4x1 W/HOUSING
DIP4/W/H/P2.0
1,5 U0RX
1,5 U0TX
5 U1RX
5 U1TX
1,5 U2TX
1,5 U2RX
UART (RS232)
5 R
5 B
5 G
1,5 VOHSYNC
1,5 VOVSYNC
U0RX
U0TX
U1RX
U1TX
U2TX
U2RX
R
B
G
VOHSYNC
VOVSYNC
C
R98
4.7K
R0603/SMD
R99
4.7K
R0603/SMD
10x2
DIP10X2/W/H/IDE/P2.54
DV33
B
U2RX
U2TX
RY/BY 15 R101
R100
4.7K
R0603/SMD
4.7K
R0603/SMD
J5
1
2
3
4
B
FOR SOFTWARE LINK
4x1 W/HOUSING
DIP4/W/H/P2.0
J6
R
B
G
VOHSYNC
VOVSYNC
1
2
3
4
5
6
7
8
ADD
CON8
A
A
Title
NOR FLASH / JTAG / UART
5
4
3
2
Size Document Number Rev
Custom MT5351RA-V2 TwinSon Chan
1
Date: Monday, September 26, 2005
Sheet 8 of 8
1

Basic Operations & Circuit Description
MODULE
There are 1 pcs panel and 8 pcs PCB including 2 pcs Y/Z Sustainer board, 2 pcs Y Drive
board, 2 pcs X (left and right) Extension PCB, 1 pcs Control (Signal Input) and 1 pcs Power
board in the Module.
SET
There are 6 pcs PCBs including 1 pcs Tuner/Audio board, 1 pcs Keypad board, 1 pcs
Remote Control Receiver board, 1 pcs L/R Speakers and 1 pcs Main (Video) board, 1 pcs ATSC
1 pcs ATSC board in the SET.

Parts position
Internal Speaker (Right) Power Supply Internal Speaker (Left)
Y-Drive Top
Y-Sustainer
Z-Sustainer
Y-Drive
Bottom
External Speaker
Terminal
X Left
Extension
Power SW
ATSC
Main
EMI Filter + AC Inlet
Local Key
remote control
receiver
Tuner/Audio
Control (Signal Input)
X Right Extension

PCB function
1. Power:
(1). Input voltage: AC 110V~240V, 47Hz~63Hz.
Input range: AC 90V(Min)~265V(Max) auto regulation.
(2). To provide power for PCBs.
2. Main board: To converter TV signals, S signals, AV signals, Y Pb/
Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to
Control board.
3. Control board: Dealing with the digital signal for output to panel.
4. Y-Sustainer / Z-Sustainer board:
(1). Receiving the signals from Control and high voltage supply.
(2). Output scanning waveform for Module.
5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning waveform
to the panel.
6. X (left and right) extension board: Output addressing signals.
7. Tuner/Audio Board: Amplifying the audio signal to the internal or external speakers
of which selected.
To convert TV RF signal to video and SIF audio signal to Main board.
8. ATSC Board: Receiver and converter ATSC TV signal to transmit to main board.

PCB failure analysis
1. CONTROL: a. Abnormal noise on screen. b. No picture.
2. MAIN : a. Lacking color, Bad color scale.
b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.
3. POWER: No picture, no power output.
4. Z - Sustainer: a. No picture.
b. Color not enough.
c. Flash on screen.
5. Y - Sustainer: Darker picture with signals.
6. Tuner/Audio : a. No voice. (Make sure status: Mute / Internal, External speaker)
b. Noise
c. No ATV signals
7. Y/Z - Sustainer: The component working temperature is about 55 o C.
If the temperature rises abnormal, this may be a error point.
8. ATSC: a. No ATSC TV signal

Basic operation of Plasma Display
1. After turning on power switch, power board sends 5Vst-by Volt to Main
IC MT8205 waiting for ON signals from Key Switch or Remote Receiver.
2. When the ON signal from Key Switch or Remote Receiver is detected, MT8205 will send
ON Control signals to Power. Then Power sends (5Vsc, 9Vsc, 12Vsc, 24V and RLY
ON, Vs ON) to PCBs working. This time VIF will send signals to display back light,
OSD on the panel and start to search available signal sources. If the audio signals
input, them will be amplified by Audio AMP and transmitted to Speakers.
3. If some abnormal signals are detected (for example: over volts, over current, over
temperature and under volts), the system will be shut down by Power off.

Main IC Specifications
- MT8205
- SiI169
- M13S128168A
- MP7720

MT8205/8203
Specifications are subject to change without notice
Application Notes
History
2004/09/12 Runma Chen for customer design-in V1.0
2004/09/30 Dragon Chen Add feature list V1.1
2004/09/30 Runma Chen Modify for PIP/POP 444 support V1.2
2004/10/01 Runma Chen PIP/POP hardware limitation-I V1.3
2004/10/18 Dragon Chen & PIP/POP hardware limitation-II & video front end component V1.4
Wen Hsu
2004/10/20 Dragon Chen Update functional block V1.5
2004/10/21 Dragon Chen Correct function block fault to V1.4 V1.6
2004/11/04 Dragon Chen 1. Delete power spec. (About power spec, please reference another document) V1.7
2. Add AC & DC characteristics
3. Add pin description
4. Add audio out mapping rule
2004/11/05 Dragon Chen Descript more detail for pin power initial state & remove some description to
another document (MT8205 product brief)
V1.8
Page 1 October, 2004

MT8205/8203
Specifications are subject to change without notice
Application Notes
MT8205/8203 Application Notes
MT8205/8203 is a highly integrated single chip for LCD TV supporting video input and output format up to HDTV.
It includes 3D comb filter TV Decoder to retrieve the best image from popular composite signals. On-chip
advanced motion adaptive de-interlacer converts accordingly the interlace video into progressive one with overlay
of a 2D Graphic processor. Optional 2 nd HDTV or SDTV inputs allows user to see multi-programs on same screen.
Flexible scalar provides wide adoption to various LCD panel for different video sources. Its on-chip audio
processor decodes analog signals from Tuner with lip sync control, delivering high quality post-processed sound
effect to customers. On-chip microprocessor reduces the system BOM and shortens the schedule of UI design by
high level C program. MT8205/8203 is a cost-effective and high performance HDTV-ready solution to TV
manufactures.
FEATURES
• Video Input
Input Multiplexing:
• Without external switch, it supports
• 1x Component,
• 1x S-video,
• 1x VGA/Component, (dual function ports)
• 1x Digital and
• 3x Composite inputs
• All the input sources can be flexibly routed to Main/PIP internally
Input Formats:
• Support VGA input up to SXGA (1280x1024@60Hz) including SOG VGA
• Support HDTV 480p/720p/1080i input
• Support DVI 24-bit RGB digital input
• Support CCIR-656/601 digital input
• TV decoder
For PIP/POP:
• Dual identical TVD on chip (Single on MT8203)
• 3D-Comb for both path.
• Dual VBI decoders for the application of V-Chip
Supporting formats:
• Support PAL (B,G,D,H,M,N,I,Nc), PAL(Nc), PAL, NTSC, NTSC-4.43, SECAM
• Automatic Luma/Chroma gain control
• Automatic TV standard detection
• NTSC/PAL Motion Adaptive 3D comb filter
• Motion Adaptive 3D Noise Reduction
• VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS
• Macrovision detection
Page 2 October, 2004

MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
• 2D-Graphic/OSD processor
• Two OSD planes. (For example, Teletext and V-Chip will occupy one planes)
• Support alpha blending among these two planes and video
• Support Text/Bitmap decoder
• Support line/rectangle/gradient fill
• Support bitblt
• Support color Key function
• Support Clip Mask
• 65535/256/16/4/2-color bitmap format OSD,
• Automatic vertical scrolling of OSD image
• Support OSD mirror and upside down
• Host Micro controller
• Turbo 8032 micro controller
• Built-in internal 373 and 8-bit programmable lower address port
• 2048-bytes on-chip RAM
• Up to 4M bytes FLASH-programming interface
• Supports 5/3.3-Volt. FLASH interface
• Supports power-down mode
• Supports additional serial interface
• IR control serial input
• Support RS232 interface
• Support single interface directly supporting SD/MS/MMC memory card
• Support 2 PWM output
• Support DDC2Bi/DDC2B/DDC1/DDCCI
• Maximum 48 programmable GPIO pins
• DRAM Controller
• Supports up to 32M-byte SDR/DDR DRAM
• Supports 16 bit DDR or 32 bit SDR/DDR bus interface
• Build in a DRAM interface programmable clock to optimize the DRAM performance
• Programmable DRAM access cycle and refresh cycle timings
• Maximum DRAM clock rate is 166MHz
• Support 3.3/2.5-Volt SDR/DDR Interface
• Video Processor
Color Management
• Flesh tone and multiple-color enhancement. (For skin, sky, and grass…)
• Gamma/anti-Gamma correction
• Color Transient Improvement (CTI)
• Saturation/hue adjustment
Contrast/Brightness/Sharpness Management
• Sharpness and DLTI/DCTI
• Brightness and contrast adjustment
• Black level extender
• White peak level limiter
• Adaptive Luma/Chroma management
De-interlacing
• Automatic detect film or video source
Page 3 July, 2004

MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
• 3:2/2:2 pull down source detection
• Advanced Motion adaptive de-interlacing
Scaling
• Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X
• Advanced linear and non-linear Panorama scaling.
• Programmable Zoom viewer
• Picture-in-Picture (PIP)
• Picture-Out-Picture (POP)
Display
• 12/10, 10/8, 8/6 Dithering processing for LCD display
• 10bit gamma correction
• Support Alpha blending for Video and two OSD planes
• Frame rate conversion
• Audio Input/Output
• 2 path TV audio in.
• Support AF/SIF decode from Tuner.
• 2 channel audio L/R digital line in.
• Total support 12 channel digital outputs optional for general stereo, 2.1 channel with subwoofer, 5.1 channel, and
headphone out.
• Audio Features
• Support BTSC/EIAJ/A2/NICAM decode
• Stereo demodulation, SAP demodulation
• Mode selection (Main/SAP/Stereo)
• Equalizer
• Sub-woofer/Bass enhancement
• MTK proprietary 3D surround processing (Virtual surround)
• Audio and video lip synchronization
• Support Reverberation
• JPEG Decoder
• Decode base-line/progressive JPEG file thru memory card i/f
• SD/MS/MMC, Maximum 1000 files (depend on DRAM size), FW is not finished yet. (10/E will be ready)
• Video Output
• 480i/576i/480p/576p/720p/1080i
• Up to (1280x1024@75Hz) (1366x768@60Hz)
• Dual-channel 6/8-bit LVDS/TTL output
• Support video output mirror and upside down
• DRAM Usage
• For features of 8205, 2pcs of 8x16 DDR166 is necessary
• For features of 8203, 2/1pcs of 8x16 DDR (limited PIP/POP features)
• Here is a comparison chart between (2xDDR) and (1xDDR)
Page 4 July, 2004

MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
DDR*1(16Mb) DDR*2(32Mb)
NR Y Y
3D-Comb Y Y
MDDi 480i/576i 1080i
PIP *Y Y
POP *Y Y
Display 1024x768 1920x1080
• For 1080i input, 8203 only support bob mode de-interlacing.
• With single DDR, we could support very limited PIP/POP mode.
• Flash Usage
• Flash is used to store FW code, fonts, bitmaps, big tables for VGA, Video, Gamma..
• In our demo system, we can support 2-4 languages within 1MB flash.
• For single country, we need around 20KB to store font data.
• For more bitmaps, we need more flash space to store them.
• 2Mbytes is recommended to build a general TV model.
• Outline
• 388-pin BGA package
• 3.3/1.8-Volt. Dual operating voltages
• 0.18um UMC process
Page 5 July, 2004

MT8205
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
BLOCK DIAGRAM
(Customer)
External
Switches
CVBS (AV)
(x3)
S
YPbPr
VGA (aRGB)
Digital
Control Signal (GPIO, …)
TTL
LVDS
Analog Front End
ADC
ADC
ADC
ADC
Digital Path
3D TVD
3D TVD
HDTVD
VGAD
Analog Path
LVDS Tx
OSD
Merge
Gamma
MUX
Main Path
MDDi
DS
MLC
PIP Path
PLC
DS
DI
Color
8032
2D Graph
OSD
US
DRAM
Dithering
DSP
Page 6 July, 2004

®
Technology
SiI 169
HDCP PanelLink Receiver
Data Sheet
Document # SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver
Data Sheet
Silicon Image, Inc.
SiI-DS-0049-B
August 2002
Application Information
To obtain the most updated Application Notes and other useful information for your design, contact your local
Silicon Image sales office. Please also visit the Silicon Image web site at www.siliconimage.com.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Trademark Acknowledgment
Silicon Image, the Silicon Image logo, PanelLink ® and the PanelLink ® Digital logo are registered trademarks of
Silicon Image, Inc. TMDS TM is a trademark of Silicon Image, Inc. VESA ® is a registered trademark of the Video
Electronics Standards Association. All other trademarks are the property of their respective holders.
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
Revision History
Revision Date Comment
A 07/18/2002 Release to Production with complete parametric information.
B 08/14/2002 Correction to DDC bus voltage level-shifting diagram; add Pb-free part number.
© 2002 Silicon Image. Inc.
ii
SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver
Data Sheet
TABLE OF CONTENTS
Functional Description .................................................................................................................................... 2
PanelLink TMDS Core ................................................................................................................................ 2
I 2 C Interface and Registers ......................................................................................................................... 2
HDCP Decryption Engine and XOR Mask .................................................................................................. 3
HDCP Keys EEPROM................................................................................................................................. 3
Panel Interface Logic and Configuration Logic ........................................................................................... 3
Electrical Specifications .................................................................................................................................. 4
Absolute Maximum Conditions.................................................................................................................... 4
Normal Operating Conditions...................................................................................................................... 4
DC Specifications........................................................................................................................................ 5
AC Specifications ........................................................................................................................................ 6
Timing Diagrams ......................................................................................................................................... 8
Input Timing............................................................................................................................................. 8
Output Timing .......................................................................................................................................... 8
Pin Descriptions.............................................................................................................................................11
Digital Output Pins......................................................................................................................................11
Configuration Pins......................................................................................................................................11
HDCP Pins ................................................................................................................................................ 12
Power Management Pins .......................................................................................................................... 12
Differential Signal Data Pins...................................................................................................................... 12
Reserved Pin............................................................................................................................................. 12
Power and Ground Pins ............................................................................................................................ 13
Feature Information ...................................................................................................................................... 14
HSYNC De-jitter Function ......................................................................................................................... 14
Clock Detect Function ............................................................................................................................... 14
Sync Detect Function ................................................................................................................................ 14
OCK_INV Function.................................................................................................................................... 14
TFT Panel Data Mapping .......................................................................................................................... 16
Power Management .................................................................................................................................. 22
HDCP Operation ....................................................................................................................................... 23
HDCP Authentication............................................................................................................................. 23
SiI 169 HDCP Implementation .............................................................................................................. 24
HDCP DDC / I 2 C Interface.....................................................................................................................24
Video Requirement for I 2 C Access ........................................................................................................ 25
I 2 C Registers.......................................................................................................................................... 25
Using SiI 169 in SiI 161B Designs ............................................................................................................ 28
EXT_RES Resistor Choice ....................................................................................................................... 29
Power Control............................................................................................................................................ 30
Receiver DDC Bus Level-Shifting ............................................................................................................. 30
Voltage Ripple Regulation ......................................................................................................................... 31
Decoupling Capacitors .............................................................................................................................. 32
ESD Protection.......................................................................................................................................... 32
Receiver Layout ........................................................................................................................................ 33
EMI Considerations................................................................................................................................... 33
PCB Thermal Design ................................................................................................................................ 33
Determining Heat Dissipation Requirements ........................................................................................ 33
Implementation Guidelines for Thermal Land Design ........................................................................... 34
Board Mounting Guidelines ................................................................................................................... 36
Stencil Design........................................................................................................................................ 37
Package........................................................................................................................................................ 38
Ordering Information..................................................................................................................................... 38
SiI-DS-0049-B
iii

SiI 169 HDCP PanelLink Receiver
Data Sheet
LIST OF TABLES
Table 1. One Pixel per Clock Mode Data Mapping ....................................................................................... 16
Table 2. Two Pixel per Clock Mode Data Mapping ....................................................................................... 16
Table 3. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2 TM Compliant.................... 17
Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 18
Table 5. 24-bit One Pixel per Clock Input with 24-bit Two Pixel per Clock Output TFT Mode...................... 19
Table 6. 18-bit One Pixel per Clock Input with 18-bit Two Pixel per Clock Output TFT Mode...................... 20
Table 7. Two Pixel per Clock Input with One Pixel per Clock Output TFT Mode.......................................... 21
Table 8. Power Management Functionality Table ......................................................................................... 22
Table 9. I 2 C Register Mapping ...................................................................................................................... 26
Table 10. I 2 C Register Definitions ................................................................................................................. 27
Table 11. Link Impedance vs EXT_RES Value (all values in Ohms) ............................................................ 29
Table 12. Power Consumption Characteristics............................................................................................. 30
Table 13. Recommended Components ........................................................................................................ 32
LIST OF FIGURES
Figure 1. SiI 169 Pin Diagram......................................................................................................................... 1
Figure 2. Functional Block Diagram................................................................................................................ 2
Figure 3. Channel-to-Channel Skew Timing................................................................................................... 8
Figure 4. Digital Output Transition Times ....................................................................................................... 8
Figure 5. Receiver Clock Cycle/High/Low Times............................................................................................ 8
Figure 6. Output Signals Setup/Hold Times.................................................................................................... 9
Figure 7. Output Signals Disabled Timing from PD# Active ........................................................................... 9
Figure 8. Output Signals Disabled Timing from Input Clock Inactive..............................................................9
Figure 9. Input Clock Active to Output Active ................................................................................................ 9
Figure 10. SCDT Timing from DE Inactive/Active......................................................................................... 10
Figure 11. TFT Two Pixels per Clock Staggered Output Timing Diagram.................................................... 10
Figure 12. I 2 C Data Valid Delay (driving Read Cycle data)........................................................................... 10
Figure 13. Block Diagram for OCK_INV ....................................................................................................... 15
Figure 14. HDCP System Architecture ........................................................................................................ 23
Figure 15. I 2 C Byte Read .............................................................................................................................. 24
Figure 16. I 2 C Byte Write .............................................................................................................................. 24
Figure 17. Short Read Sequence ................................................................................................................. 25
Figure 18. Design Using SiI 161B or SiI 169 ................................................................................................ 29
Figure 19. DDC Bus Voltage Level-Shifting using Fairchild NDC7002N ...................................................... 30
Figure 20. Voltage Regulation using Texas Instruments TL431 ................................................................... 31
Figure 21. Voltage Regulation using National Semiconductor LM317.......................................................... 31
Figure 22. Decoupling and Bypass Schematic ............................................................................................. 32
Figure 23. Decoupling and Bypass Capacitor Placement ............................................................................32
Figure 24. DVI to Receiver Routing - Top View ............................................................................................ 33
Figure 25. Bottom View of Thermally Enhanced 100-pin TQFP Package.................................................... 34
Figure 26. TQFP Thermal Land Design on PCB .......................................................................................... 35
Figure 27. Thermal Pad Via Grid .................................................................................................................. 36
Figure 28. Recommended Stencil Design .................................................................................................... 37
Figure 29. Package Diagram ........................................................................................................................ 38
iv
SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver
Data Sheet
General Description
The SiI 169 Receiver uses PanelLink Digital
technology to support HDTV and high-resolution
digital displays for DTV and PC applications. It
features High-bandwidth Digital Content Protection
(HDCP) for secure delivery of high-definition video in
consumer electronics products.
The SiI 169 comes with integrated, pre-programmed
HDCP keys, greatly simplifying manufacturing and
providing the highest level of security. For improved
ease of use, the SiI 169 has enhanced jitter
tolerance and a low-power standby mode.
PanelLink Digital technology is the world’s leading
DVI solution, providing a digital interface solution that
is easy to implement and cost-effective. PanelLink
further simplifies the display interface design by
resolving many of the system level issues associated
with high-speed mixed signal circuits.
Features
• Integrated 25-165MHz PanelLink core to support
VGA to UXGA resolutions
• Supports HDTV resolutions (720p/1080i)
• Integrated HDCP decryption engine for viewing
protected content
• Pre-programmed HDCP keys provide highest
level of key security, simplify manufacturing
• Enhanced jitter tolerance
• Time staggered data output for reduced ground
bounce
• High Skew Tolerance: 1 full input clock cycle
(6ns at 165MHz)
• Backwards compatible with SiI 161B
• Sync Detect for “Hot Plugging”
• Flexible low power modes with automatic power
down when input clock is inactive
• Low power 3.3V core operation
• Compliant with DVI 1.0
• Standard and Pb-free packages (see page 38).
SiI 169 Pin Diagram
ODD 8-bits RED
ODD 8-bits GREEN
ODD 8-bits BLUE
QO2 51
QO3 52
QO4 53
QO5 54
QO6 55
QO7 56
OVCC 57
OGND 58
QO8 59
QO9 60
QO10 61
QO11 62
QO12 63
QO13 64
QO14 65
QO15 66
VCC 67
GND 68
QO16 69
QO17 70
QO18 71
QO19 72
QO20 73
QO21 74
QO22 75
50 QO1
OGND 76
QO23 77
49 QO0
CONTROLS
OVCC 78
48 HSYNC
AGND 79
47 VSYNC
RX2+ 80
46 DE
OUTPUT
CLOCK
OGND
ODCK
OVCC
45
44
43
RX2- 81
AVCC 82
AGND 83
CTL3
42
AVCC 84
OCK_INV
HS_DJTR
GND
VCC
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVCC
OGND
QE15
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
SiI 169
100-pin TQFP
(Top View)
RX1+ 85
RX1- 86
AGND 87
AVCC 88
AGND 89
RX0+ 90
RX0- 91
AGND 92
RXC+ 93
RXC- 94
AVCC 95
EXT_RES 96
PVCC 97
PGND 98
RESERVED 99
DIFFERENTIAL SIGNALS
EVEN 8-bits RED
PLL
QE14
26
SCL 100
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
QE13
QE12
QE11
QE10
QE9
QE8
OGND
OVCC
QE7
QE6
QE5
QE4
QE3
QE2
QE1
QE0
PDO#
SCDT
STAG_OUT
VCC
GND
PIXS
SDA
PD#
RESET#
EVEN 8-bits GREEN
EVEN 8-bits BLUE CONFIG. PINS
Figure 1. SiI 169 Pin Diagram
SiI-DS-0049-B 1

SiI 169 HDCP PanelLink Receiver
Data Sheet
Functional Description
The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content Protection
(HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP. Pre-programmed HDCP
keys simplify manufacturing while providing the highest level of security. There is no need to use encrypted keys,
program EEPROMs, or cure epoxy coating.
Figure 2 shows the functional blocks of the chip.
STAG_OUT
PIXS
OCK_INV
HS_DJTR
RESET#
PD#
PDO#
Registers
--------------
Configuration Logic
HDCP
Decryption
Engine
HDCP
Keys
EEPROM
SCLS
SDAS
I 2 C
Slave
CTL3
RXC±
RX0±
RX1±
RX2±
EXT_RES
PanelLink
TMDS TM
Digital
Core
24
/
encrypted
data
XOR
Mask
control
24
/
unencrypted
data
Panel
Interface
Logic
QE[23:0]
QO[23:0]
ODCK
DE
HSYNC
VSYNC
SCDT
PanelLink TMDS Core
Figure 2. Functional Block Diagram
The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a display enable (DE) signal that drives high
when video pixel data is present. The SCDT signal is output when there is active video on the DVI link and the
PLL has locked on to the video. SCDT can be used to trigger external circuitry, indicating that an active video
signal is present; or used to place the device outputs in power down when no signal is present (by tying SCDT to
PDO#). A resistor tied to the EXT_RES pin is used for impedance matching.
I 2 C Interface and Registers
The SiI 169 uses a slave I 2 C interface, capable of running at 400kHz, for communication with the host. HDCP
authentication is managed by reading and writing to registers through the I 2 C interface. This bus, called DDC in
the DVI specification, is also tied to the EDID EEPROM that contains information about the display’s capabilities
(resolution, aspect ratio, etc.). The I 2 C address of the SiI 169 is 74h as specified by HDCP. This interface is not
5V tolerant and it is recommended that a voltage level shifter be used between the SiI 169 and the DVI connector
as the DDC bus is specified to support 5V signaling.
2 SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver
Data Sheet
HDCP Decryption Engine and XOR Mask
The HDCP decryption engine contains all the necessary logic to decrypt an incoming video signal on a pixel-bypixel
basis. The host system microcontroller initiates an authentication sequence with the receiver to initialize the
SiI 169 HDCP decryption engine. Upon successful completion of the authentication process, the SiI 169 is ready
to decrypt the incoming video via the XOR mask.
Encrypted and unencrypted video will be sent at different times. Therefore the host HDCP transmitter uses the
CTL3 signal to indicate to the SiI 169 receiver whether the incoming video is encrypted or not.
HDCP Keys EEPROM
The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In this way the
keys are provided the highest level of protection as required by the HDCP specification. Silicon Image manages all
aspects of the key purchasing and programming. There is no need for the customer to purchase HDCP keys from
the licensing authority. For security reasons, the keys cannot be read out of the device.
Samples of the SiI 169 are available with the B1 public keys as listed in the back of the HDCP specification.
These are marked with a -PUB part number as noted in the Ordering Information section. Make sure to request
either “Public” or “Production” keys when requesting samples. Before receiving samples of the SiI 169 with
production keys a customer must have signed the HDCP license agreement.
Panel Interface Logic and Configuration Logic
Unencrypted video data is sent to the display logic by way of a 48-bit output interface. The functionality of this
interface is affected by several of the externally strapped configuration logic options as follows.
• The data output can be presented in either one pixel per clock or two pixels per clock format, depending on
the PIXS configuration setting.
• The polarity of the output clock ODCK can be inverted to accommodate both rising- and falling-edge clocking
through the OCK_INV configuration setting.
• Using the STAG_OUT configuration setting, the odd and even data output groups can be staggered in time to
reduce EMI.
• The HS_DJTR configuration setting can compensate for host-side jitter on the HSYNC input to the transmitter.
• The PD# and PDO# inputs select chip power down modes and allow for disabling of the outputs to the panel.
The RESET# input must be in the HIGH state during normal operation, in both HDCP and non-HDCP modes. Its
primary purpose is to reset the digital block circuitries, including the HDCP engine, and registers at initial chip
power-up time. The VSYNC, HSYNC, DE, and CTL3 signals will be driven low while RESET# is asserted. If it is
necessary to disable the HDCP engine while leaving the chip fully operational for reception of unencrypted video, use the
software reset feature located at bit 0 of register 0xFF by setting it to “1”.
SiI-DS-0049-B 3

ESMT
M13S128168A
Revision History
Revision 0.1 (15 Jan. 2002)
- Original
Revision 0.2 (19 Nov. 2002)
-changed ordering information & DC/AC characteristics
Revision 0.1 Revision 0.2
M13S128168A - 5T
M13S128168A - 6T
M13S128168A - 6T
M13S128168A - 7.5AB
Revision 0.3 (8 Aug. 2003)
-Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003)
-Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003)
-Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003)
-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.
Revision 1.2 (12 Jan. 2004)
-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.
Revision 1.3 (12 Mar. 2004)
-Add Cas Latency=2; 2.5
Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004
Revision : 1.3 1/48

ESMT
DDR SDRAM
2M x 16 Bit x 4 Banks
M13S128168A
Double Data Rate SDRAM
Features
• JEDEC Standard
• Internal pipelined double-data-rate architecture, two data access per clock cycle
• Bi-directional data strobe (DQS)
• On-chip DLL
• Differential clock inputs (CLK and CLK )
• DLL aligns DQ and DQS transition with CLK transition
• Quad bank operation
• CAS Latency : 2; 2.5; 3
• Burst Type : Sequential and Interleave
• Burst Length : 2, 4, 8
• All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
• Data I/O transitions on both edges of data strobe (DQS)
• DQS is edge-aligned with data for reads; center-aligned with data for WRITE
• Data mask (DM) for write masking only
• V DD = 2.375V ~ 2.75V, V DDQ = 2.375V ~ 2.75V
• Auto & Self refresh
• 7.8us refresh interval
• SSTL-2 I/O interface
• 66pin TSOPII package
Operating Frequencies :
PRODUCT NO. MAX FREQ VDD PACKAGE
M13S128168A -5T
M13S128168A -6T
200MHz
166MHz
2.5V TSOPII
Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004
Revision : 1.3 2/48

ESMT
M13S128168A
Functional Block Diagram
CLK
CLK
CKE
Address
Clock
Generator
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank D
Bank C
Bank B
Bank A
CS
RAS
CAS
WE
Command Decoder
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Output
Buffer
DM
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
x16 x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004
Revision : 1.3 3/48

Monolithic Power Systems
General Description
The MP7720 is a mono 20W Class-D Audio
Amplifier. It is one of MPS’ second generation
of fully integrated audio amplifiers which
dramatically reduces solution size by
integrating the following:
• 180mΩ power MOSFETs
• Start up / shut down pop elimination
• Short circuit protection circuits
• Mute / Stand By
The MP7720 utilizes a single ended output
structure capable of delivering 20W into 4Ω
speakers. MPS Class-D Audio Amplifiers
exhibit the high fidelity of a Class A/B amplifier
at efficiencies greater than 90%. The circuit is
based on the MPS’ proprietary variable
frequency topology that delivers excellent
PSRR, fast response time and operates on a
single power supply.
Ordering Information
Part Number ∗ Package Temperature
MP7720DS SOIC8 -40°C to + 85°C
MP7720DP PDIP8 -40°C to + 85°C
EV0030
Evaluation Board
∗ For Tape & Reel use suffix - Z (e.g. MP7720DS-Z)
∗ For Lead Free use suffix - LF (e.g. MP7720DS-LF)
MP7720
20W Class D Mono
Single Ended Audio Amplifier
Features
PRELIMINARY INFORMATION
• 20W output at V DD =24V into a 4Ω load
• THD+N = 0.04% @ 1W, 8Ω
• 93% efficiency at 20W
• Low noise (190µV typical)
• Switching Frequency to 1MHz
• 9.5V to 24V operation from single supply
• Integrated Start Up and Shut Down
Pop Elimination Circuit
• Thermal protection
• Integrated 180mΩ switches
• Mute / Standby-mode (Sleep)
• Tiny 8 Pin SOIC or PDIP Package
• Evaluation Board Available
Applications
• Surround Sound DVD Systems
• Televisions
• Flat Panel Monitors
• Multimedia computers
• Home stereo
20
VDD
7.5V to 24V
10
5
OFF
ON
EN
PIN
VDD
PGND
2
1
8Ω
4Ω
NIN
BS
%
0.5
AGND
SW
0.2
0.1
0.05
0.02
Audio
Input
4 Ω or 8 Ω
0.01
100m 200m 500m 1
W
2 5 10 20
60m 30
Figure 2: THD+N vs. Power (24V, 1KHz)
Figure 1: Typical Application Circuit
MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 1

Monolithic Power Systems
Absolute Maximum Ratings (Note 1)
Supply Voltage V DD
26V
BS Voltage
V SW -0.3V to V SW +6.5V
Enable Voltage V EN
-0.3V to 6V
V SW , V PIN , V NIN -1V to V DD +1V
AGND to PGND -0.3V to 0.3V
Junction Temperature 150°C
Lead Temperature 260°C
Storage Temperature -65°C to 150°C
MP7720
20W Class D Mono
Single Ended Audio Amplifier
PRELIMINARY INFORMATION
Recommended Operating Conditions (Note 2)
Supply Voltage V DD
9.5V to 24V
Operating Temperature T A -40°C to 85°C
Package Thermal Characteristics
Thermal Resistance Θ JA (SOIC8)
Thermal Resistance Θ JC (SOIC8)
Thermal Resistance Θ JA (PDIP8)
Thermal Resistance Θ JC (PDIP8)
105°C/W
50°C/W
95°C/W
55°C/W
Table 1: Electrical Characteristics (V DD =24V, V EN =5V, T A =25°C)
Parameters Condition Typ Max Units
Supply Current
Standby Current V EN = 0V 1 5 µA
Quiescent Current 1.5 3.0 mA
Output Drivers
SW On Resistance Sourcing and Sinking 0.18 Ω
Short Circuit Current Sourcing and Sinking 5.0 A
Inputs
PIN, NIN Input Common Mode
V
0 DD
Voltage Range
2
V DD -1.5 V
PIN, NIN Input Current V PIN =V NIN =12V 1 5 µA
EN Enable Threshold Voltage
V EN Rising 1.4 2.0 V
V EN Falling 0.4 1.2 V
EN Enable Input Current V EN = 5V 1 µA
Thermal Shutdown
Thermal Shutdown Trip Point T J Rising 150 °C
Thermal Shutdown Hysteresis 30 °C
Table 2: Operating Specifications (Circuit of Figure 3, V DD =24V, V EN =5V, T A =25°C)
Standby Current V EN = 0V 130 µA
Quiescent Current 13 mA
Power Output
f=1KHz, THD+N = 10% , 4Ω Load 20 W
f=1KHz, THD+N = 10% , 8Ω Load 10 W
THD+ Noise
P OUT =1W, f=1KHz, 4Ω Load
P OUT =1W, f=1KHz, 8Ω Load
0.08
0.04
%
%
Efficiency
f =1KHz, P OUT =1W, 4Ω Load 90 %
f =1KHz, P OUT =1W, 8Ω Load 95 %
Maximum Power Bandwidth 20 KHz
Dynamic Range 93 dB
Noise Floor A-Weighted 190 µV
Power Supply Rejection f=1KHz 60 dB
Note 1. Exceeding these ratings may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 2

Monolithic Power Systems
MP7720
20W Class D Mono
Single Ended Audio Amplifier
PRELIMINARY INFORMATION
R3
100KΩ
R2
100KΩ
Audio Input
ON
OFF
C3, 5.6nF
C2
4.7µF,
16V
VDD
EN
PGND
PIN
MP7720
NIN
BS
AGND
R4, 82KΩ
SW
R6
10KΩ
C5
1µF, 35V
C7, 0.1µF
D2, 6.2V
L1, 10µH
D1
1A, 30V
C6
470µF, 35V
VDD
9.5 to 24V
C9
1000µF
25V
C8
0.47µF
50V Metal
R L
4Ω
C1
1µF, 16V
R1, 10KΩ
C4
10pF
C10
390pF
R5
10kΩ
Figure 3: 20W Mono Typical Application Circuit
MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 3

0. Warnings and Cautions
Product Specification of PDP Module
WARNING indicates hazards that may lead to death or injury if ignored.
CAUTION indicates hazards that may lead to injury or damage to property if ignored.
WARNING
1) This product uses a high voltage (450 V max.). Do not touch the circuitry of this product with your hands when
power is supplied to the product or immediately after turning off the power. Be sure to confirm that the voltage
is dropped to a sufficiently low level.
2) Do not supply a voltage higher than that specified to this product. This may damage the product and may cause a
fire.
3) Do not use this product in locations where the humidity is extremely high, where it may be splashed with water,
or where flammable materials surround it. Do not install or use the product in a location that does no satisfy the
specified environmental conditions. This may damage the product and may cause a fire.
4) If a foreign substance (such as water, metal, or liquid) gets inside the product, immediately turn off the power.
Continuing to use the products it may cause fire or electric shock.
5) If the product emits smoke, an abnormal smell, or makes an abnormal sound, immediately turn off the power. If
noting is displayed or if the display goes out during use, immediately turn off the power. Continuing to use the
product as it is may cause fire or electric shock.
6) Do not disconnect or connect the connector while power to the product is on. It takes some time for the voltage
to drop to a sufficiently low level after the power has been turned off. Confirm that the voltage has dropped to a
safe level before disconnecting or connecting the connector. Otherwise, this may cause fire, electric shock, or
malfunction.
7) Do not pull out or insert the power cable from/to an outlet with wet hands. It may cause electric shock.
8) Do not damage or modify the power cable. It may cause fire or electric shock.
9) If the power cable is damaged, or if the connector is loose, do not use the product; otherwise, this can lead to fire
or electric shock.
10) If the power connector or the connector of the power cable becomes dirty or dusty, wipe it with a dry cloth.
Otherwise, this can lead to fire.

Product Specification of PDP Module
USE
1) Because this product uses a high voltage, connecting or disconnecting the connectors while power is supplied to
the product may cause malfunctioning. Never connect or disconnect the connectors while the power is on.
Immediately after power has been turned off, a residual voltage remains in the product. Be sure to confirm that
the voltage has dropped to a sufficiently low level.
2) Watching the display for a long time can tire the eyes. Take a break at appropriate intervals.
3) PDP ’s brightness and contrast ratio is lower than that of the CRT. The picture is dimmer with surrounding light
and better for viewing in dark condition.
4) Do not cover or wrap the product with a cloth or other covering while power is supplied to the product.
5) Before turning on power to the product, check the wiring of the product and confirm that the supply voltage is
within the rated voltage range. If the wiring is wrong or if a voltage outside the rated range is applied, the
product may malfunction or be damaged.
6) Do not store this product in a location where temperature and humidity are high. This may cause the product to
malfunction. Because this product uses a discharge phenomenon, it may take time to light (operation may be
delayed) when the product is used after it has been stored for a long time. In this case, it is recommended to light
all cells for about 2hours (aging).
7) If the glass surface of the display becomes dirty, wipe it with a soft cloth moistened with a neutral detergent. Do
not use acidic or alkaline liquids, or organic solvents.
8) Do not tilt or turn upside down while the module package is carried, the product may be damaged.
9) This product is made from various materials such as glass, metal, and plastic. When discarding it, be sure to
contact a professional waste disposal operator.
Repair and Maintenance
Because this product combines the display panel and driver circuits in a single module, it cannot be repaired or
maintained at user’s office or plant. Arrangements for maintenance and repair will be determined later

Product Specification of PDP Module
1. GENERAL DESCRIPTION
DESCRIPTION
The PDP42V6#### is a 42-inch 16:9 color plasma display module with resolution of 852(H) 480(V) pixels.
This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.
FEARURES
High peak brightness (1000cd/m 2 Typical) and high contrast ratio (3000:1 Typical) enables user to create
high performance PDP SETs.
APPLICATIONS
Public information display
Video conference systems
Education and training systems

Product Specification of PDP Module
ELECTRICAL INTERFACE OF PLASMA DISPLAY
The PDP42V6#### requires only 8bits of digital video signals for each RGB color.
In addition to the video signals, six different DC voltages are required to operate the display.
The PDP42V6#### is equipped with P-CUBE function which analyzes display signals to optimize system
control factor for showing the best display performance.
GENERAL SPECFICATIONS
Model Name
Number of Pixels
Pixel Pitch
Cell Pitch
Display Area
Outline Dimension
Pixel Type
Number of Gradations
Weight
Aspect Ratio
Peak Brightness
Contrast Ratio
Power Consumption
Life-time
: PDP42V6#### (42V6#### Model)
: 852(H) 480(V) (1pixel=3 RGB cells)
: 1080 (H) 1080 (V)
: 367 (H) 1080 (V) (Green Cell basis)
: 920.1(H) 518.4(V) 0.5mm
: 1005(H) 597(V) 61(D)1mm
: RGB Closed type
: (R)256 (G)256 (B)256 (16.7 Mega colors)
: 14.8 Kg 0.5 Kg (Net 1EA)
111 Kg 5 Kg (5EA/1BOX)
: 16:9
: Typical 1000cd/ (1/25 White Window)
: Average 60:1 (In a bright room with 150Lux at center)
: Typical 3000:1 (In a dark room 1/25 White Window pattern at center)
: Typical 220 W (Full White)
: more than 60,000 Hours of continuous operation
Life-time is defined as the time when the brightness level becomes half of its initial value.
Display Dot Diagram
Pixel Pitch(width)
1st
pixel
column
1.080
2nd
pixel
column
Cell pitch
R:0.338
G:0.367
B:0.374
851th
pixel
column
cell
852th
pixel
column
pixel
1st pixel
row
2nd pixel
row
3rd pixel
row
pitch(height)
1.080
R
R
R
G
G
G
B
B
B
R
R
R
G
G
G
B
B
B
R
R
R
G
G
G
B
B
B
R
R
R
G
G
G
B
B
B
479th pixel
row
R
G
B
R
G
B
R
G
B
R
G
B
480th pixel
row
R
G
B
R
G
B
R
G
B
R
G
B

Product Specification of PDP Module
7. CONNECTORS and CONNECTIONS
Power Input Connector
‣ Connector P3001 Pin Assignment
Pin No. Symbol Pin No. Symbol
1
2
3
4
Vs
Vs
nc
GND
5
6
7
8
GND
Va
GND
+5V
Module side connector : 1-1123723-8 (Header)
Mating Connector : 1-1123722-8 (Housing)
Connector Supplier : AMP
8
7
6
5
1-1123723-8 Pin numbers
(Top View, viewed from the pin connection side)
4
3
2
1
‣ Connector P2005 Pin Assignment
Pin No. Symbol Pin No. Symbol
1 VS
6 GND
2 VS
7 GND
3 VS
8 GND
4 nc
9
nc
5 GND
10 nc
Module side connector : 1-1123723-10 (Header)
Mating Connector : 1-1123722 –10 (Housing)
Connector Supplier : AMP
10
9
8
7
6
5
4
3
2
1
1-1123723-10 Pin numbers
(Top View, viewed from the pin connection side)
‣ Connector P2006 Pin Assignment
Pin No. Symbol Pin No. Symbol
1
GND 3
5V
2
GND 4
5V
Module side connector : 1-1123723-4 (Header)
Mating Connector : 1-1123722-4 (Housing)
Connector Supplier : AMP
4
3
1-1123723-4 Pin numbers
(Top View, viewed from the pin connection side)
2
1

Pin Assignment
Product Specification of Power Supply Unit
8. Input/Output pin assignment & specification
CN808
CN804
CN803
CN809
CN802 #1 ~#2
: 30V or 24V
#3 ~ #4
: GND
CN801
#1 ~ #4
: +5Vctrl
#5 ~ #8
: GND
#1 : 9Vsc
#2 : 9Vsc
#3 : GND
#4 : 5Vsc
#5 : 5Vsc
#6 : 5Vsc
#7 : GND
#8 : GND
#9 : GND
#1 ~ #3 : 5Vsc
#4 ~ #6 : GND
#7, #8 : 12Vsc
#9, #10 : GND
#11, #12 : NC
#1 : 9Vsc
#2: GND
#1 : ACD
#2 : RLY ON
#3 : 5Vst_by
#4 : GND
#5 : Vs ON
#6 : 5VD
#7 : NC
CN01
4 3 2 1
#1 ~#2
: 5Vctrl
#3 ~ #4
: GND
Selection S/W
24V 30V
From inlet
CN805
10 9 8 7 6 5 4 3 2 1
CN806
#1 : Va
#2 : Va
#3 : GND
#4 : GND
#5 : GND
#6 : GND
#7 : NC
#8 : Vs
#9 : Vs
#10 : Vs
Normal : On/Off with Vsc B/D
CN02
Before connecting with S/W
* PSU operation method S/W
Live
Neutral
CN03
8 7 6 5 4 3 2 1
#1 : Vs
#2 : Vs
#3 : NC
#4 : GND
#5 : GND
#6 : Va
#7 : GND
#8 : +5V
Auto : Automatic On/Off
without Vsc B/D
Live
Neutral
After connecting with S/W
CN807

Adjustment detail
Product Specification of Power Supply Unit
9. Adjustment detail
CN808
CN804
4 3 2 1
CN805
10 9 8 7 6 5 4 3 2 1
CN806
8 7 6 5 4 3 2 1
CN807
CN803
Selection S/W
24V 30V
CN809
Selection S/W
CN802
CN801
Normal
(Mode1)
Auto
(Mode2)
Auto(Mode2) : Driving without
interface B/D
Normal(Mode1) : Driving with interface B/D
CN01
CN02
Live
Neutral
CN03
Live
Neutral

Product Specification of PDP Module
8. LABEL
LABEL Sticking Position
Coner Plate
E/X Tube
3211QKE008A
P/N
(carved)
Y-SUS
Z-SUS
X left
CONTROLLER
Signal Input
(R,G,B,H/Vsync.)
X right
Identification Label : LABEL
7.0
2.5
Model Name
Bar Code (Code 128, Contains the manufacture No.)
Manufacture No.
The trade name of LG Electronics
Manufactured date (Year & Month)
Manufactured place

Trouble Shooting Manual of PDP Module
- Introduction
- Precautions
- Basic
- Trouble shooting

1. Introduction
COMPOSITION OF PDP BOARDS
42” V6 MODEL.
PSU
Y-DRIVE
TOP
Z-SUS B/D
Y-SUS
B/D
IPM
Y-DRIVE
BOTTOM
X-LEFT B/D
COF
CONTROL B/D
X-RIGHT B/D

1. Introduction
Definitions
Definition of MODULE position
* Back side of module
long 1
Exhaust
hole
short 1
long 2
short 2
COF long2-1 •••••••• COF long 2-7
Identification label
6####
402K242V6000266.ASLGA
2004.02
Model Name
Bar Code (Code 128, Contains the manufacture No.)
Manufacture No.
The trade name of LG Electronics
Manufactured date (Year & Month)
The place Origin
Model Suffix

1. Introduction
Voltage label (Attached on back side of module)
Part No. label (Attached on board)
Vsetup
-Vy
Vsc
BOARD ASS`Y
PART NO.
BOARD NAME
PCB PART NO.
BOARD SERIAL NO.
COF serial No. label (attached on COF)
COF SERIAL NO.

1. Introduction
Terms of defect
8

2. Precaution
Safety precautions
Be sure to read this before service. When using/ handling this PDP module, Please pay attention to the
below warning and cautions.
1. Before repairing there must be a preparation for 10 min.
2. Do not impress a voltage that higher than represented on the product.
3. Since PDP module uses high voltages, Be careful a electric shock
and after removing power some current remains in drive circuit.
so you can touch circuit after 1 min.
4. Drive circuits must be protected from static electricity.
5. The PDP module must be Moved by two man.
6. Be careful with short circuit of PDP boards when measuring any voltages.
Before request service
1. Check panel surface and appearance of B/D.
2. Check the model label. Whether it is boards of same model with label.
3. Before requesting Service, please inform us a detail defect phenomenon and history of module.
it can be helpful to us for a smooth sevice.
Ex) COF long 2-1 fail ,address 1 line open, Y b/d problem , mis-discharge.
9

2. Precaution
Handle with care (COF)
COF is the most important component in the PDP module.
Even a little imperfection of COF can make a serious screen problem.
SCRATCHING TEARING BEING PUSHED
BENDING
CHOPING

3. Basic
1. X B/D
: receiving LOGIC signal from CONTROL B/D and make ADDRESS
PULSE(generates Address discharge)by ON/OFF operation,
and supplies this waveform to COF(data)
Signal part
Power part
X LEFT B/D
X RIGHT B/D
Lift up lock as shown
in narrow.
Pull COF
as shown in narrow.

3. Basic
2. Z sustain B/D
: make SUSTAIN PULSE and ERASE PULSE that generates
SUSTAIN discharge in panel by receiving LOGIC signal from
CONTROL B/D.
this waveform is supplied to panel through FPC(Z).
*composed with IPM,FET,DIODE, electrolytic capacitor ,E/R coil.
* IPM (Intelligent Power Module)
E/R(Energy recovery)
Separate the fixed Screw of Z-Board.
Pull out Lock as shown in arrow.
Condition in Lock part is pulled
Pull FPC Connector
as shown in arrow.
12

3. Basic
3. Y drive B/D
1) This is a path to supply SUSTAIN ,RESET waveform which made
from Y SUSTAIN B/D to panel through SCAN DRIVER IC.
2) Supply a wave form that select Horizontal electrode (Y SUSTAIN electrode)
sequentially.
- potential difference is 0V between GND and Vpp of DRIVER IC
in SUSTAIN period.
- being generated potential difference between GND and Vpp only
in SCAN period.
* In case of 42” V6 use DRIVER IC IC 8 EA (TOP, BOTTOM: each 4EA)
13

3. Basic
4. Y sustain B/D
: generates SUSTAIN,RESET waveform, Vsc(SCAN)voltage.
and supplies it Y DRIVER B/D.
* Composed with IPM,DIODE, electrolytic capacitor ,FET.
5. Control Board
: creates signal processing (Contour noise,reduction ISM,..)
and an order of many FET on/off of each DRIVER B/D with
R,G,B each 8bit input.
* Use 3.3V/5V 2 kinds of power .
14

3. Basic
6. DC/DC Converter part
DC/DC con.
part
: Being impressed 5V, Va ,Vs,
DC/DC converter makes
5V,Va,Vs,Vset_up,Vsc
which is essential for each B/D.
There is no DC/DC B/D in
model 40 /42 (1 POWER B/D).
* 50 60 embedded DC/DC B/D
separately because of high power
consumption.
15

3. Basic
7. FPC (Flexible Printed Circuit)
: supply a driving waveform to PANEL by connecting a PAD
electrode of PANEL with PCB(Y and Z).
* there is two type of this for Y B/D. One is single-sided,
another is double-side. These are having pattern on it
* for Z B/D, there is no pattern , single-sided, and Beta
type(all of copper surface).
8. FFC (Flat Flexible Cable)
: for connecting a Logic signal between B/D and B/D.
*There is 0.5mm pitch,50pin type
1mm pitch ,30pin type.
16

3. Basic
9. COF (Chip On Film)
: supply a waveform which made from X B/D to panel and select
a output pin that is controlled by COF when be on or off.
96 output pin per IC.
the more the resolution higher, the less spare space where
can set IC on it in B/D. without using IC PACKAGE,
we can use a BARE IC , so we can get IC with LOW COST
because we do not solder IC on PCB directly,
a soldering defect rate decrease.
* composition
Bare IC
1) FPC + Heat /Sink
⇒ FPC for COF must have a Low Spec decline with getting damp
2) CHIP resistor + CHIP CAPACITOR
3) BARE IC (STV7610A/WAF) + GOLD WIRE/AL WIRE
4) EPOXY MOLDING
* 42 V6 COF is the same as 42V5.

3. Basic
10. IPM(Intelligent Power Module)
: composition
HEATSINK,CAPACITOR
DIODE
IC LINEAR
RESISTORTANSISTOR,FETS.
: description
Attached at Z B/D and Y B/D, make Sustain waveform.
Sustainer : supply a square wave to panel to make a video.
IPM
18

4. Trouble shooting.
what
Fast check
kind of
updefect?
defect
Check model No. of module ,all connectors and cables.
No display?
Check panel appearance Check PSU output (Va,Vs,5v) Check Y, Z b/dinput voltage
Replace ctrl b/d
Replace Y, Z b/d
vertical defect?
Check panel appearance Check COF Replace X b/d Replace ctrl b/d
Horizontal defect?
Check FPC Replace Y drv b/d Replace Y sus b/d Replace ctrl b/d
Mis –discharge
on screen?
Replace Y drv b/d Replace Y sus b/d Replace ctrl b/d
19

4. Trouble shooting.
Logical judgment
what kind of defect?
What kind of defect ?
No display?
Please follow the no display trouble shooting.
vertical defect?
Bar defect appeared?
Please follow bar defect trouble shooting.
Horizontal defect?
Line defect
Please follow the line defect trouble shooting.
Mis –discharge
on screen?
Please follow the mis discharge trouble shooting.
20

4. Trouble shooting.
No display
1. Connector
Confirm every Connector (PSU, Y-SUS, CTRL, Z-SUS)
module may not be normal by mis-connection which can not send signal and power.
Also Mis connection for a long time has a specific b/d failed.
21

4. Trouble shooting.
2. Exhaust tip Crack
Confirm exhausting Tip and find Crack with naked eyes to check vacuum state.
If there is problem replace the module .
in case of vacuum breakdown, module makes a shaking noise because of inside gas ventilation.
(there may be a small crack which could not see with naked eyes. And this noise is different from Capacitor noise. )
NORMAL
CRACKED
22

4. Trouble shooting.
3. PSU(Power Supply Unit)
1. Check each unit part of PSU inside with naked eyes.
(capacitor, FET, a kind of IC, resistor)
2. Check FUSE and SW1 (on Normal).
3. Check Output voltage which is converted from AC V
to DC V.
SW1 Normal
voltage Check (5V, Va, Vs)
When PSU Protection occurred. Check Short
between Y-SUS, Z-SUS B/D .
Confirm
input voltage
if not same
Adjust
voltages
Fuse open check
Multi-meter Touch point
(5V, Va ,Vs must accord with Module Label)
Vs Voltage ADJ
(Vs : About 180 ~195 V)
Va, 5V(VCC) Voltage ADJ
Va : About 55 ~65 V
5V(VCC) : 5V~5.5V)

4. Trouble shooting.
4. Ctrl B/D
Diode
1. Confirm LED D17(flashing) ,13 lighting
2. If not CHECK OSC X1 output.
3. Check CTRL input voltage
(CONNECTOR P300)
4. CHECK 3.3V, 5V,15V.
5. Check IC 11 3.3V
IC 3 2.5V
Input voltage
OSC(X1)
Probe
Touching
point
Check IC 11,13
DMM +
Check oscillating state.
(normal 100 MHZ)
Be careful with physical shock.
DMM – (GND)

4. Trouble shooting.
5. Y-sus B/D
1. Check FUSE [FS1(5v) ,FS2(Vs)].
2. Check voltages(Vsetup,-Vy, Vscw)
3. Check DIODE between GND and Y SUS output.
[SUSUP(OC2) SUSDN(OC1)].
forward=0.4 ,reverse=OVERLOAD.
4. Check whether output voltages agrees
with voltage that represented in label.
Vscw
-Vy
Vsetup
FS2
setdn
setup
FS1
25

4. Trouble shooting.
Check whether output voltages agrees with voltage that represented in label.
Check diode value GND between Y-SUS output.
Normal diode value= 0.4 (forward)
Normal diode value = OL (reverse)

4. Trouble shooting.
6. Z-sus B/D
1. Check the FUSE.
2. Check input voltages.(Va, 5V,15V)
3. Check FPC out put diode value.
4. Check ramp waveform.
Check the FUSE
Check input voltages
5V FUSE
Va FUSE 6.3A
Vs FUSE 2A or 4A

4. Trouble shooting.
Variable resistance of Z RAMP
waveform slope.
Check FPC output diode value.
caution: check certainly after removing FPC.
Normal diode value=0.375(forward)
Normal diode value=OVER LOAD(reverse)

4. Trouble shooting.
Power protection
It is power protection when power is off automatically within 2~3 min. from power on.
Power protection function protect the boards when occurred short on circuits of PDP module or power problem.
If can not impress power even after replacing PSU, find out where the short occurred.
* PSU makers.
DAEGIL PSU
UNICON PSU
29

4. Trouble shooting.
Vertical defect (bar)
1. Connector
Check COF connector.
If not connected well,it will Make a bar defect .
Check here
Bar
Check here
Off
2. Checking COF
Confirm whether COF was torn. And then check input of COF resistor and IC.
Tearing
COF 6 is torn partly
30

4. Trouble shooting.
Checking address COF input of resistor and IC
COF resistor checking
Check the both side of resistor With Digital multi meter(DMM) .
If the resistor is normal, the resistor value will be 10.2 ~ 10.8
31

4. Trouble shooting.
Checking address COF input of resistor and IC
IC input checking
Inside of IC , there is 4 ea diodes which separated in 2 series .
(input 2, output 2)
*how to check
1.contact DMM - terminal to a right terminal of condenser(GND)
and DMM + terminal to a right terminal of IC, normal value 0.66 (fig.1)
2.contact DMM - terminal to Output terminal of resistor, and
DMM + terminal to a right terminal of IC , normal value 0.73 (fig.2)
Fig. 1 Fig. 2

4. Trouble shooting.
3. Ctrl B/D
CTRL B/D supplies video signal to COF. So if there is a bar defect on screen,
It may be the ctrl b/d problem.
A flow of address signal
In this figure, we can easily suppose
what will be appeared on screen when a specific part failed.
Buffer
IC
96 output

4. Trouble shooting.
Vertical defect (line)
1 line open or short
This phenomenon is due to COF IC inside short or adherence part of the Film and rear panel electrode problem.
In this case, replace the panel.
1 electrode open
1 line open
Line open or short with same distance.
This is MCM of Ctrl b/d defect. MCM can not be replaced separately. So replace the ctrl b/d.
MCM (Multi Chip Module)

4. Trouble shooting.
line defect from each parts
• Case 1: Buffer IC fail
COF IC 1,2 192 line(96+96) open.
COF IC 3,4 64 line open (with fixed interval there is on,off ……. Repetition)
16 line open
• case 2 : Array resistor fail
COF IC1 16 line , COF IC2 16 line open
• case3 : COF IC fail
96 line open.
96 line open

4. Trouble shooting.
Horizontal (bar)
Most horizontal defects can be repaired. In case of adherence part of the Film and rear panel
electrode defect or panel electrode open,short , replace the panel.
1. Connector
It can make a horizontal bar that connector on Y b/d and Z b/d did not plugged well. Because sustain voltage
can not be supplied to panel. So check connectors (FPC, Y drv –Y drv) first.
Disconnected
Horizontal bar
Disconnected
Screen off

4. Trouble shooting.
2. Scan IC check
Check diode value of the right side part of output pin.
DMM + DMM -
Check here with DMM(either forward or reverse is ok)
37

4. Trouble shooting.
Horizontal (line)
1. Check FPC
In case of horizontal 1 or more line, it is due to FPC or panel inside .
ctrl b/d, Y b/d is just normal.
FPC electrode open
Panel electrode
Insulation break down
Horizontal 1 line.
2. Check scan IC
Check with same method that presented in Horizontal (bar).
38

4. Trouble shooting.
How to check IPM
Forward : test 1 GND() , Sus-out()
2 Sus-out(),Vs()
3 ER-DN(),ER-COM()
4 ER-COM(),ER-UP()
when each 4 TEST Diode value is over 0.4V => OK
Reverse : test 1 GND() , Sus-out()
2 Sus-out(),Vs()
3 ER-DN(),ER-COM()
4 ER-COM(),ER-UP()
when each 4 nodes TEST Diode value is infinity => OK
Specially, the value of ER-UP,COM,DN in the Y/Z board, should be
checked all of them. but, the terminal of Vs,Sus-out,GND,
we must aware to know after check one of IPM because it is parallel.
if no problems, check 15V(Y,Z B/D) with GND, Forward value 0.3V,
Reverse value infinite. If no problems,
40

Product Specification of PDP Module
CAUTION
General
1) Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as an
inclined surface. The product may fall off or fall over, causing injuries.
2) When moving the product, be sure to turn off the power and disconnect all the cables. While moving the
product, watch your step. The product may be dropped or fall, leading to injuries of electric shock.
3) Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as an
inclined surface. The product may fall off or fall over, causing injuries.
4) Before disconnecting cable from the product, be sure to turn off the power. Be sure to hold the connector when
disconnecting cables. Pulling a cable with excessive force may cause the core of the cable to be exposed or
break the cable, and this can lead to fire or electric shock.
5) This product should be moved by two or more persons. If one person attempts to carry this product alone, he/she
may be injured.
6) This product contains glass. The glass may break, causing injuries, if shock, vibration, heat, or distortion is
applied to the product.
7) The temperature of the glass surface of the display may rise to 80°C or more depending on the conditions of use.
If you touch the glass inadvertently, you may be burned.
8) Do not poke or strike the glass surface of the display with a hard object. The glass may break or be scratched. If
the glass breaks, you may be injured.
9) If you glass surface of the display breaks or is scratched, do not touch the broken pieces or the scratches with
bare hands. You may be injured.
10) Do not place an object on the glass surface of the display. The glass may break or be scratched.

Spare Part List for PDP4210EA
Item
Part Number Part Description Usage
/ Unit
Unit
1 E6205-001003 42” ED PDP Module 1 Piece
2 900-420103-01B 42” Glass Filter 1 piece
3 E7801-100001 Main PCBA 1 set
4 E7801-100002 Audio PCBA 1 set
5 771S42D101-01 ATSC PCBA 1 set
7 771-42D111-01 Control PCBA 1 set
8 771-42D111-02 IR PCBA 1 set
9 E4101-027001 Power Switch 1 piece
10 E4801-116002 Speaker 2 piece
11 E3301-028005 Speaker Terminal (without cable) 1 piece
12 E3404-157004 AC Power Cord 1 piece
13 E3421-926080 LVDS Cable 1 piece
14 E3421-925049 Connection Cable 1 1 piece
15 E3421-926083 Connection Cable 3 1 piece
16 E3421-926084 Connection Cable 4 1 piece
17 E3421-927001 Power Switch Cable 1 1 piece
18 E3421-927002 Power Switch Cable 2 1 piece
19 E3421-926081 Control PCBA Cable 1 piece
20 E3421-926094 IR PCBA Cable 1 piece
21 E7501-051007 Remote Control 1 set
22 E7301-010002 AAA size Battery 1 pair

Spare Part List for PDP4210EA
Item
Part Number Part Description Usage
/ Unit
Unit
23 200-42D131-MTK02AV Front Plastic Frame 1 piece
24 277-42D101-01S Function Knob 1 piece
25 263-42D101-01S Power Lens 1 piece
26 269-42D101-01L IR Lens 1 piece
27 481-42D107-01S PCBA Shield Box 1 piece
28 483-42D103-01 PCBA Shield Top Cover 1 piece
29 436-42D118-01S Terminal Frame 1 piece
30 402-42D114-01S Metal Back Cover 1 piece
31 423-42D11E-01S Power Switch Metal Frame 1 piece
32 510-42D101-MTU02K Top Carton Box 1 piece
33 511-42D111-01K Bottom Carton Box 1 piece
34 300-42D106-02C Top Cushion 1 piece
35 300-42D105-02C Bottom Cushion 1 piece
36 244-34B811-01 Carton Box Handle 2 piece
37 310-504004-01 Poly bag for Main Unit 1 piece
38 310-111404-07V Poly bag for Instruction Manual 1 piece
39 580-P42AAEM-TU02L Instruction Manual 1 piece
40 388-42SB04-01H Power Socket Plate 1 piece
41 388-42D103-01H Caution Plate 1 piece
42 387-42AA01-MTU02H Model Plate 1 piece
43 388-42SB02-01H Speaker Terminal Plate 1 piece
44 384-42D103-MTU01H Terminal Plate 1 piece
45 590-42AA01-04 Warranty Sheet 1 piece

Spare Part List for PDP4210EA
Item
Part Number Part Description Usage
/ Unit
Unit
46 579-42D102-09 Model Plate Serial Number 1 piece
47 579-42AA01-05 Bar Code Label 1 pair
48 579-42D103-02 ON/OFF Label 1 piece
49 568-P46T02-02 Warning Label 1 piece
50 734-BP0302-01 Duck Feet Stand 1 set

If you forget your V-Chip Password
- Omnipotence V-Chip Password: 8205.
Using the “Change Password” item
When enter the “Parental” menu, select “Change Password”.
Press ▲ or ▼ button to highlight the “Change Password” item.
Press Enter button to confirm and pop up a menu.
Use 0~9 buttons input the omnipotence password(8205), then Press Enter button to enter and
pop up a menu.
Use 0~9 buttons input your new password.
Press ▼ button to move to confirm blank.
Use 0~9 buttons input your new password again.
Press Enter button to confirm
-Suggest: Change to your familiar Password again.

Software upgrade
Process of update MT8205AE
Preparing :
1) Connect RS232-VGA download line, One connector is connected to VGA connect port of
Plasma TV while another side is connected to PC COM port.
2) Store the MtkTool into the PC .
Downloading :
3) Turn on AC power and wait TV entering standby mode, while the color of the power
indicator is Red.
4) Execute MTKtool and select the chipset as MT8205. (the software of MTKtool will be sent to
your side)
5) Select current COM port. (please try to check the COM port of your PC).

6) Choose the bit rate as 115200.
7) Select the update binary by pressing browse button. For exemple,the binary file name is
PDP4210EA_VIORE_XXXXXX_XXXX_VXX.bin. (this update firmware will be sent
to your side)

8) Press Upgrade button and start update process.

9) The update process is successful as the progress bar is 100%. After the update process is ok,
turn off power and wait indicator light is off. Turn on power and TV can work.
Checking
It is needed to check the version of the firmware for MT8205AE which has been
download into the Plasma TV .
Press Menu button of the remote control for a little long time and the OSD menu
for Factory Setting is appeared on the screen .
Use the remote control and select the mode of the Factory Setting then enter the
mode of the Factory Setting .
Use the remote control and select the mode of Firmware Version and then enter the
mode of Firmware Version . It is easy to be found the version of the current firmware
for MT8205AE is as the following : “Firmware Version : VXX ”
Process of update MT5351AG
Preparing :
1) Connect RS232-VGA download line, One connector is connected to VGA connect port of
Plasma TV while another side is connected to PC COM port.
2) Store the MtkTool into the PC
Downloading :
3) Turn on AC power switch of the Plasma TV and then press the button “standby” of the remote
control . The image could be found on the screen of the Plasma TV while the color of the
power indicator is green . (the mode of the Plasma TV will be standby mode if after turn on
the main power switch only . )
4) Execute MTKtool and select the chipset as MT5351AG. (the software of MTKtool will be sent
to your side)

5) Select current COM port. (please try to check the COM port of your PC).
6) Choose the bit rate as 115200.
7) Select the update binary by pressing browse button. For exemple,the binary file name is

XXXX_PDP4210EA_ATSC_IT_000000XX_X_P.bin. (this update firmware will be sent
to your side)
8) Press Upgrade button and start update process.

9) The update process is successful as the progress bar is 100%. After the update process is ok,
turn off power and wait indicator light is off. Turn on power and TV can work.
Checking :
It is needed to check the version of the firmware for MT5351AG which has been
download into the Plasma TV .
Press Menu button of the remote control and the main OSD menu is appeared on
the screen .
Use the remote control and select the mode of the adjustment .
Use the remote control and select the mode of DTV
Entry the mode of DTV
Input “0000” (zero , zero , zero , zero) of the remote control while the Plsama TV is
under the above condition . Then enter the mode of factory after input the digits .
It is easy to be found the version of the current firmware for MT5351AG is
“XXXX_PDP4210EA_ATSC_IT_000000XX_X_P”under the mode of factory .
PC
PDP
RS232-VGA download line
RXD
TXD
GND
2
3
5
11
4
5
RXD
TXD
GND
D-Sub 9(RS232)
D-Sub 15A(VGA)