PIC24FJ128GA310 Family Errata - Microchip

PIC24FJ128GA310 FAMILY 

PIC24FJ128GA310 Family 

Silicon Errata and Data Sheet Clarification 

The PIC24FJ128GA310 Family devices that you have 

received conform functionally to the current Device Data 

Sheet (DS39996F), except for the anomalies described 

in this document. 

The silicon issues discussed in the following pages are 

for silicon revisions with the Device and Revision IDs 

listed in Table 1. The silicon issues are summarized in 

Table 2. 

The errata described in this document will be addressed 

in future revisions of the PIC24FJ128GA310 Family 

silicon. 

Note: 

This document summarizes all silicon 

errata issues from all revisions of silicon, 

previous as well as current. Only the 

issues indicated in the last column of 

Table 2 apply to the current silicon 

revision (B2). 

Data Sheet clarifications and corrections start on page 5, 

following the discussion of silicon issues. 

The silicon revision level can be identified using the 

current version of MPLAB ® IDE and Microchip’s 

programmers, debuggers, and emulation tools, which 

are available at the Microchip corporate web site 

(www.microchip.com). 

For example, to identify the silicon revision level using 

MPLAB IDE in conjunction with MPLAB ICD 2 or 

PICkit 3: 

1. Using the appropriate interface, connect the 

device to the MPLAB ICD 2 programmer/ 

debugger or PICkit 3. 

2. From the main menu in MPLAB IDE, select 

Configure>Select Device, and then select the 

target part number in the dialog box. 

3. Select the MPLAB hardware tool 

(Debugger>Select Tool). 

4. Perform a “Connect” operation to the device 

(Debugger>Connect). Depending on the development 

tool used, the part number and Device 

Revision ID value appear in the Output window. 

Note: 

If you are unable to extract the silicon 

revision level, please contact your local 

Microchip sales office for assistance. 

The DEVREV values for the various 

PIC24FJ128GA310 Family silicon revisions are shown 

in Table 1. 

TABLE 1: 

SILICON DEVREV VALUES 

Part Number Device ID (1) Revision (2) 

Revision ID for Silicon 

PIC24FJ64GA306 

46C0h 


46C4h 


46C8h 


46C2h 

4 


46C6h 

PIC24FJ128GA310 

46CAh 

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration 

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. 

2: Refer to the “PIC24FJXXXDA1/DA2/GB2 Families Flash Programming Specification” (DS39970) for 

detailed information on Device and Revision IDs for your specific device. 

B2 

2012 Microchip Technology Inc. DS80532B-page 1


TABLE 2: 

Module 

A/D Conversion 

During Sleep 

A/D Auto-Scan 

Mode 

SILICON ISSUE SUMMARY 

Feature 

Threshold 

Detect 

A/D Threshold 

Detect 

Item 

Number 

Issue Summary 

1. Auto-scan feature may not trigger correctly in Sleep 

mode. 

2. In Auto-scan mode, the highest number A/D channel 

may not cause interrupt. 

Affected 

Revisions (1) 

A/D A/D Accuracy 3. Noise injection on A/D input pin during A/D operation X 

(when reading a high-impedance input). 

VBTBOR VBAT BOR 4. VBTBOR (CW3) is not functional. X 

RTCC RTCC Operation 5. During a Power on Reset, the RTCC may be enabled. X 

A/D DNL 6. DNL will not meet data sheet specifications and possible X 

missing codes. 

Deep Sleep IPD 7. IPD maximum numbers will be higher than in the data X 

sheet. 

A/D DMA PIA Mode 8. DMA with A/D in PIA mode will not work X 

Reset 

Low-Voltage/ 9. POR and BOR bits will get set after Reset. 

Retention Sleep 

Note 1: Only those issues indicated in the last column apply to the current silicon revision. 

B2 

X 

X 

DS80532B-page 2 

2012 Microchip Technology Inc.


Silicon Errata Issues 

Note: 

1. Module: A/D Conversion During Sleep 

When the auto-scan feature of the Threshold 

Detect is enabled (AD1CON5 = 1), automatic 

scan may fail when these conditions occur 

together: 

• The Device is in Sleep mode, and 

• Timer1 is selected as the sample trigger clock 

source (AD1CON1 = 0110). 

Timer1 and other timers will function correctly as 

sample triggers in other power-saving modes, 

such as Idle mode. 

Work around 

Use INT0 to trigger the A/D in Sleep mode. 

Affected Silicon Revisions 

B2 

X 

2. Module: A/D Auto-Scan Mode 

In Auto-Scan mode (AD1CON5 = 1), when 

the Auto-Scan Interrupt mode bits are set to ‘11’ 

(AD1CON5 = 11), the highest number channel 

selected for scanning in AD1CSSL, or 

AD1CSSH, may not trigger an interrupt on a valid 

comparison. 

Work around 

Add a dummy channel to the scanning sequence. 

For example, when scanning AN0 and AN1, set 

AD1CSSL to 0x0007 or 0x8003, or whatever is 

practical given the implementation. 

Also, if the highest number channel needs to be 

scanned, the AD1CHITH bit can be polled to 

observe a valid comparison. 


B2 

X 

Corrections are shown in bold. Where 

possible, the original bold text formatting. 

3. Module: A/D Accuracy 

Noise injection on the A/D input pin during A/D 

operation (when reading a high-impedance input). 

Work around 

Increase the sample time for the channel that is 

being converted or reduce the source impedance. 


B2 

X 

4. Module: VBTBOR 

VBTBOR (CW3) is not functional. 

Work around 

None. 


B2 

X 

5. Module: RTCC 

During a Power-on Reset, the RTCC may be 

enabled. 

Work around 

To ensure that the RTCC is not enabled, make 

sure to clear the RTCEN after a POR. This is 

recommended whether RTCC is used or not. 

After a POR, execute the code below to disable 

the RTCC: 

MOV #NVMKEY,W1 ;move the address of 

NVMKEY into W1 

MOV #0x55, W2 

MOV W2, [W1] ;start 55/AA sequence 

MOV #0xAA, W3 

MOV W3, [W1] 

BSET RCFGCAL,#13 ;set the RTCWREN bit 

RCFGCALbits.RTCEN=0; 


B2 

X 



6. Module: A/D 

The DNL will not meet the data sheet 

specification; the DNL will be 1.5. There may be 

possible missing codes in 12-bit mode in 

locations: 511, 1023, 1535, 2047, 2559, 3071, 

3583. 

Work around 

None. 


B2 

X 

7. Module: Deep Sleep 

The IPD maximum number for Deep Sleep may not 

meet the data sheet specification (DC70). 

The maximum values for Deep Sleep at 3.3V will 

be 2.5 µA. 

Work around 

None. 


B2 

X 

8. Module: A/D 

The A/D will not work with DMA in PIA mode. 

Work around 

None. 


B2 

X 

9. Module: Reset 

When the device is in Low-Voltage/Retention 

Sleep (Sleep with CW1 = 0 and RETEN = 1), 

if a Master Clear Reset is given, the POR 

(RCON) and BOR (RCON) bits will get set 

after the Reset. 

Work around 

Use registers, such as DSGPR0 or DSGPR1, to 

indicate the device was in Low-Voltage/Retention 

Sleep before the MCLR Reset is given. 


B2 

X 




Data Sheet Clarifications 

The following typographic corrections and clarifications 

are to be noted for the latest version of the device data 

sheet (DS39996F): 

Note: 

Corrections are shown in bold. Where 

possible, the original bold text formatting 

has been removed for clarity. 

1. Module: Real Time Clock and Calendar 

In the data sheet, the beginning chapter note for 

Section 22.0 is corrected as follows: 

Note: 

This data sheet summarizes the features 

of this group of PIC24F devices. It is not 

intended to be a comprehensive reference 

source. For more information on the 

Real-Time Clock and Calendar, refer to 

the “PIC24F Family Reference Manual”, 

Section 56. RTCC with External 

Power Control (RTCC) (DS39745). 



2. Module: Special Features 

On Page 342, in Register 29-5: DEVID: Device 

ID Register, the contents of the bits are 

changed as shown below in bold: 

REGISTER 29-5: 

DEVID: DEVICE ID REGISTER 

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 

— — — — — — — — 

bit 23 bit 16 

R R R R R R R R 

FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 

bit 15 bit 8 

R R R R R R R R 

DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 

bit 7 bit 0 

Legend: R = Readable bit U = Unimplemented bit 

bit 23-16 Unimplemented: Read as ‘1’ 

bit 15-8 FAMID: Device Family Identifier bits 

0100 0110 = PIC24FJ128GA310 Family 

bit 7-0 DEV: Individual Device Identifier bits 

1100 0000 = PIC24FJ64GA306 

1100 0010 = PIC24FJ128GA306 

1100 0100 = PIC24FJ64GA308 

1100 0110 = PIC24FJ128GA308 

1100 1000 = PIC24FJ64GA310 

1100 1010 = PIC24FJ128GA310 





On page 336, in Register 29-2: CW2: Flash 

Configuration Word 2, a new bit has been added 

for CW2, BOREN1, as shown below in bold: 

REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2 

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 

— — — — — — — — 

bit 23 bit 16 

R/PO-1 r-1 r-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 

IESO r r ALTVRF1 ALTVRF0 FNOSC2 FNOSC1 FNOSC0 

bit 15 bit 8 

R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 

FCKSM1 FCKSM0 OSCIOFCN IOL1WAY BOREN1 r POSCMD1 POSCMD0 

bit 7 bit 0 

Legend: 

r = Reserved bit 

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ 

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 


bit 15 IESO: Internal External Switchover bit 

1 = IESO mode (Two-Speed Start-up) is enabled 

0 = IESO mode (Two-Speed Start-up) is disabled 

bit 14-13 Reserved: Always maintain as ‘1’ 

bit 12-11 ALTVRF: Alternate VREF/CVREF Pins Selection bits 

00 = Voltage reference input, A/D = RB0/RB1, Comparator = RB0/RB1 

01 = Voltage reference input, A/D = RB0/RB1, Comparator = RA9, RA10 

10 = Voltage reference input, A/D = RA9/RA10, Comparator = RB0, RB1 

11 = Voltage reference input, A/D = RA9/RA10, Comparator = RA9, RA10 

bit 10-8 FNOSC: Initial Oscillator Select bits 

111 = Fast RC Oscillator with Postscaler (FRCDIV) 

110 = Reserved 

101 = Low-Power RC Oscillator (LPRC) 

100 = Secondary Oscillator (SOSC) 

011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 

010 = Primary Oscillator (XT, HS, EC) 

001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 

000 = Fast RC Oscillator (FRC) 

bit 7-6 FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits 

1x = Clock switching and Fail-Safe Clock Monitor are disabled 

01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 

00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled 

bit 5 OSCIOFCN: OSCO Pin Configuration bit 

If POSCMD = 11 or 00: 

1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 

0 = OSCO/CLKO/RC15 functions as port I/O (RC15) 

If POSCMD = 10 or 01: 

OSCIOFCN has no effect on OSCO/CLKO/RC15. 




CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) 

bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit 

1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been 

completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 

0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been 

completed 

bit 3 BOREN1: BOR Override bit 

This bit should be set/cleared based on the BOREN (CW3) setting 

1 = BOR is enabled (CW3, BOREN = 1) 

0 = BOR is disabled (CW3 , BOREN = 0) 

Allowed combinations are shown below: 

BOREN (CW3): BOREN1 (CW2) 

11 = BOR is enabled 

10 = Reserved 

01 = Reserved 

00 = BOR is disabled 

bit 2 Reserved: Always maintain as ‘1’ 

bit 1-0 POSCMD: Primary Oscillator Configuration bits 

11 = Primary Oscillator mode is disabled 

10 = HS Oscillator mode is selected 

01 = XT Oscillator mode is selected 

00 = EC Oscillator mode is selected 





On Page 338, in Register 29-3: CW3: Flash 

Configuration Word 3, bit 12 has been modified 

as shown below in bold: 

REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3 

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 

— — — — — — — — 

bit 23 bit 16 

R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 

WPEND WPCFG WPDIS BOREN WDTWIN1 WDTWIN0 r SOSCSEL 

bit 15 bit 8 

R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 

VBTBOR WPFP6 (3) WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 

bit 7 bit 0 

Legend: PO = Program Once bit r = Reserved bit 




bit 15 WPEND: Segment Write Protection End Page Select bit 

1 = Protected code segment upper boundary is at the last page of program memory; the lower 

boundary is the code page specified by WPFP 

0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper 

boundary is the code page specified by WPFP 

bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit 

1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected (1) 

0 = Last page and Flash Configuration Words are write-protected provided WPDIS = ‘0’ 

bit 13 WPDIS: Segment Write Protection Disable bit 

1 = Segmented code protection is disabled 

0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and 

WPFPx Configuration bits 

bit 12 BOREN: Brown-out Reset Enable bit (also see CW2 BOREN1) 

1 = BOR is enabled (all modes except Deep Sleep) (BOREN1 = 1) 

0 = BOR is disabled (BOREN1 = 0) 

Allowed combinations are shown below: 

BOREN (CW3): BOREN1 (CW2) 

11 = BOR is enabled 

10 = Reserved 

01 = Reserved 

00 = BOR is disabled 

Note 1: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word page, the 

Configuration Word page is protected. 

2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1). 

3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be 

maintained as ‘0’. 




CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) 

bit 11-10 WDTWIN: Watchdog Timer Window Width Select bits 

11 =25% 

10 =37.5% 

01 =50% 

00 =75% 

bit 9 Reserved: Always maintain as ‘1’ 

bit 8 

SOSCSEL: SOSC Selection bit 

1 = SOSC circuit is selected 

0 = Digital (SCLKI) mode (2) 

bit 7 VBTBOR: VBAT BOR Enable bit 

1 = VBAT BOR is enabled 

0 = VBAT BOR is disabled 

bit 6-0 WPFP: Write-Protected Code Segment Boundary Page bits (3) 

Designates the 256 instruction words page boundary of the protected code segment. 

If WPEND = 1: 

Specifies the lower page boundary of the code-protected segment; the last page being the last 

implemented page in the device. 

If WPEND = 0: 

Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. 

Note 1: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word page, the 

Configuration Word page is protected. 

2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1). 

3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be 

maintained as ‘0’. 

5. Module: Timer 1 

On Page 197, the first paragraph has been 

changed as shown below: 

The Timer1 module is a 16-bit timer that can 

operate as a free-running, interval timer/counter. 

Timer1 can operate in three modes: 

6. Module: Pin Diagrams 

On page 3, 4 and 5, the note “Pinouts are 

subject to change” has been removed. 

7. Module: Pin Diagrams 

The T1CK has been removed from RB9 ports 

from all the following pinouts: 

Page 3, on 64-pin devices, the Pin 22 has been 

modified to remove T1CK as AN9/RP9/SEG30/ 

COM6/PMA7/CN27/RB9. 



COM6/CN27/RB9. 



COM6/CN27/RB9. 

Page 8, on Table 1, Pin L4 has been modified to 

remove T1CK as AN9/RP9/COM6/SEG30/ 

CN27/RB9. 

8. Module: Guidelines for Getting Started 

with 16-Bit Microcontrollers 

Page 27, Table 1-4, the T1CK has been 

removed. 



2012 Microchip Technology Inc. DS80532B-page 11 

9. Module: Memory Organization 

On page 57, Table 4-22, ANSA10 and ANSA9 are added in bold as 

shown below: 

TABLE 4-22: 

ANALOG CONFIGURATION REGISTER MAP 

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 

ANCFG 04DE — — — — — — — — — — — — — VBG6EN VBG2EN VBGEN 0000 

ANSA 04E0 — — — — — ANSA10 ANSA9 — ANSA7 (1) ANSA6 (1) — — — — — — 06C0 

ANSB 04E2 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 FFFF 

ANSC 04E4 — — — — — — — — — — — ANSC4 (1) — — — — 0010 

ANSD 04E6 — — — — ANSD11 ANSD10 — — ANSD7 ANSD6 — — — — — — 0CC0 

ANSE 04E8 — — — — — — ANSE9 (2) — ANSE7 ANSE6 ANSE5 ANSE4 — — — — 02F0 

ANSG 04EC — — — — — — ANSG9 ANSG8 ANSG7 ANSG6 — — — — — — 03C0 

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 

Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. 

2: These bits are unimplemented in 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital functionality on RE9. 

All 

Resets 

PIC24FJ128GA310 FAMILY


10. Module: I/O Ports 

On page 169, Register 11-1, ANSA10 and 

ANSA9 are added in bold as shown below: 


ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER 

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 U-0 

— — — — — ANSA10 ANSA9 — 

bit 15 bit 8 

R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 

ANSA7 (1) ANSA6 (1) — — — — — — 

bit 7 bit 0 

Legend: 




bit 10-9 ANSA: Analog Function Selection bits (1) 

1 = Pin is configured in Analog mode; I/O port read is disabled 

0 = Pin is configured in Digital mode; I/O port read is enabled 

bit 8 Unimplemented: Read as ‘0’ 

bit 7-6 ANSA: Analog Function Selection bits (1) 

1 = Pin is configured in Analog mode; I/O port read is disabled 

0 = Pin is configured in Digital mode; I/O port read is enabled 


Note 1: 

These bits are not available in 64-pin and 80-pin devices. 



2012 Microchip Technology Inc. DS80532B-page 13 

11. Module: Memory Organization 

On Page 63, Table 4-31, LVDCON has changed to HLVDCON, as shown 

in bold below: 

TABLE 4-31: 

SYSTEM CONTROL (CLOCK AND RESET) REGISTER MAP 

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 

RCON 0740 TRAPR IOPUWR — RETEN — DPSLP CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1 

OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note 2 

CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 0100 

OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 

REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 

HLVDCON 0756 LVDEN — LSIDL — — — — — DIR BGVST IRVST — LVDL3 LVDL2 LVDL1 LVDL0 0000 

RCON2 0762 — — — — — — — — — — — r VDDBOR VDDPOR VBPOR VBAT Note 1 

Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. 

Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section 7.0 “Resets” for more information. 

2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 9.0 “Oscillator Configuration” for more information. 

All 

Resets 

PIC24FJ128GA310 FAMILY


12. Module: I/O Ports 

On Page 184, Register 11-20, SPI2 has 

changed to SPI1, as shown in bold below: 

REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 

— — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 

bit 15 bit 8 


— — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 

bit 7 bit 0 

Legend: 




bit 13-8 SCK1R: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits 


bit 5-0 SDI1R: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits 

On Page 185, Register 11-22, T1CKx has changed to 

SCKRx, as shown in bold below: 

REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 


— — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 

bit 15 bit 8 


— — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 

bit 7 bit 0 

Legend: 




bit 13-8 SCK2R: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits 


bit 5-0 SDI2R: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits 




13. Module: Electrical Characteristics 

On Page 370, Table 32-19, the FOSC parameter 

for the oscillator min. frequency changed 

(OS10), as shown in bold below: 

TABLE 32-19: 

AC CHARACTERISTICS 

EXTERNAL CLOCK TIMING REQUIREMENTS 

Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) 

Operating temperature-40°C £ TA £ +85°C for Industrial 

Param 

No. 

Symbol Characteristic Min Typ (1) Max Units Conditions 

OS10 FOSC External CLKI Frequency 

(External clocks allowed 

only in EC mode) 

DC 

4 

Oscillator Frequency 3.5 

4 

10 

4 

31 

— 

— 

— 

— 

— 

— 

— 

32 

8 

10 

8 

32 

8 

33 

MHz 

MHz 

MHz 

MHz 

MHz 

MHz 

kHz 

EC 

ECPLL 

XT 

XTPLL 

HS 

HSPLL 

SOSC 

OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for 

FOSC value 

OS25 TCY Instruction Cycle Time (2) 62.5 — DC ns 

OS30 

OS31 

TosL, 

TosH 

TosR, 

TosF 

External Clock in (OSCI) 

High or Low Time 

External Clock in (OSCI) 

Rise or Fall Time 

0.45 x TOSC — — ns EC 

— — 20 ns EC 

OS40 TckR CLKO Rise Time (3) — 6 10 ns 

OS41 TckF CLKO Fall Time (3) — 6 10 ns 

Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only 

and are not tested. 

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are 

based on characterization data for that particular oscillator type, under standard operating conditions, with 

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation 

and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an 

external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time 

limit is “DC” (no clock) for all devices. 

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the 

Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). 



14. Module: Electrical Characteristics 

On Page 360, the text in Figure 32-1 has been 

modified to PIC24FJXXXGA3XX, as shown in 

bold below: 

FIGURE 32-1: 

PIC24FJ128GA310 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 

3.6V 3.6V 

PIC24FJXXXGA3XX 

Voltage (VDD) 

2.2V 

VBOR 

2.2V 

VBOR 

Frequency 

32 MHz 

Note: 

VCAP (nominal On-Chip Regulator output voltage) = 1.8V. 

15. Module: 12-Bit A/D Converter with 

Threshold Scan 

On Page 307, Register 24-7, the text has been 

modified, as shown in bold below: 


ANCFG: A/D BAND GAP REFERENCE CONFIGURATION 

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 

— — — — — — — — 

bit 15 bit 8 

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 

— — — — — VBG6EN VBG2EN VBGEN 

bit 7 bit 0 

Legend: 




bit 2 

bit 1 

bit 0 

VBG6EN: A/D Input VBG/6 Enable bit 

1 = Band gap voltage, divided by six reference (VBG/6), is enabled 

0 = Band gap, divided by six reference (VBG/6), is disabled 

VBG2EN: A/D Input VBG/2 Enable bit 

1 = Band gap voltage, divided by two reference (VBG/2), is enabled 

0 = Band gap, divided by two reference (VBG/2), is disabled 

VBGEN: A/D Input VBG Enable bit 

1 = Band gap voltage reference (VBG) is enabled 

0 = Band gap reference (VBG) is disabled 




16. Module: Real-Time Clock and Calendar 

(RTCC) 

On Page 276, in Section 22.1, a note has been 

added as shown in bold: 

22.1 RTCC Source Clock 

The user can select between the SOSC crystal 

oscillator, LPRC internal oscillator or an external 

50 Hz/60 Hz power line input as the clock reference 

for the RTCC module. This gives the user 

an option to trade off system cost, accuracy and 

power consumption, based on the overall system 

needs. If using SOSC for time-sensitive 

application, do not enable the LCD pin 

(SEG17) adjacent to the SOSCI pin. 

Note: 

Do not enable the LCD segment pin, 

SEG17 on RD0, if the SOSC is used for 

time-sensitive applications. Avoid 

high-frequency switching adjacent to 

the SOSCO and SOSCI pins. 



17. Module: A/D Converter 

On Page 300, Register 24-1, the SSRC 

bits have one more mode (0110), as shown in 

bold text below: 

REGISTER 24-1: AD1CON1: A/D CONTROL REGISTER 1 

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 

ADON — ADSIDL DMABM (1) DMAEN MODE12 FORM1 FORM0 

bit 15 bit 8 

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS 

SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE 

bit 7 bit 0 

Legend: U = Unimplemented bit, read as ‘0’ 

R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit 


bit 15 ADON: A/D Operating Mode bit 

1 = A/D Converter module is operating 

0 = A/D Converter is off 


bit 13 ADSIDL: Stop in Idle Mode bit 

1 = Discontinue module operation when device enters Idle mode 

0 = Continue module operation in Idle mode 

bit 12 DMABM: Extended DMA Buffer Mode Select bit(1) 

1 = Extended Buffer mode: Buffer address is defined by the DMAnDST register 

0 = PIA mode: Buffer addresses are defined by the DMA controller and AD1CON4 

bit 11 DMAEN: Extended DMA/Buffer Enable bit 

1 = Extended DMA and buffer features are enabled 

0 = Extended features are disabled 

bit 10 MODE12: 12-Bit Operation Mode bit 

1 = 12-bit A/D operation 

0 = 10-bit A/D operation 

bit 9-8 FORM: Data Output Format bits (see formats following) 

11 = Fractional result, signed, left-justified 

10 = Absolute fractional result, unsigned, left-justified 

01 = Decimal result, signed, right-justified 

00 = Absolute decimal result, unsigned, right-justified 

bit 7-4 SSRC: Sample Clock Source Select bits 

1xxx = Unimplemented, do not use 

0111 = Internal counter ends sampling and starts conversion (auto-convert). Do not use in 

Auto-Scan mode 

0110 = Timer1 in Sleep (for Auto-Scan mode) 

0101 =TMR1 

0100 =CTMU 

0011 =TMR5 

0010 =TMR3 

0001 =INT0 

0000 = The SAMP bit must be cleared by software to start conversion 

Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN = 1). 





AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED) 


bit 2 ASAM: A/D Sample Auto-Start bit 

1 = Sampling begins immediately after last conversion; SAMP bit is auto-set 

0 = Sampling begins when SAMP bit is manually set 

bit 1 SAMP: A/D Sample Enable bit 

1 = A/D Sample-and-Hold amplifiers are sampling 

0 = A/D Sample-and-Hold amplifiers are holding 

bit 0 DONE: A/D Conversion Status bit 

1 = A/D conversion cycle has completed 

0 = A/D conversion has not started or is in progress 

Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN = 1). 



APPENDIX A: 

DOCUMENT 

REVISION HISTORY 

Rev A Document (11/2011) 

Initial release of this document. Includes silicon issues 1 

(A/D Conversion During Sleep), 2 (A/D Auto-Scan 

Mode), 3 (A/D Accuracy), 4 (VBTBOR) and 5 (RTCC). 

Added data sheet clarification 1 (Section 22.0 Real 

Time Clock and Calendar). 

Rev B Document (4/2012) 

Included changes to silicon issue 1 (A/D Conversion 

During Sleep) and added silicon issues 8 (A/D) and 

9 (Reset), and added data sheet clarifications 

2 (Special Features), 3 (Special Features), 4 (Special 

Features), 5 (Timer1), 6 (Pin Diagrams), 7 (Pin Diagrams), 

8 (Guidelines for Getting Started with 16-Bit 

Microcontrollers), 9 (Memory Organization), 10 (I/O 

Ports), 11 (Memory Organization), 12 (I/O Ports), 

13 (Electrical Characteristics), 14 (Electrical Characteristics), 

15 (12-Bit A/D Converter with Threshold 

Scan), 16 (Real-Time Clock and Calendar – RTCC) 

and 17 (A/D Converter). 



Note the following details of the code protection feature on Microchip devices: 

• Microchip products meet the specification contained in their particular Microchip Data Sheet. 

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the 

intended manner and under normal conditions. 

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our 

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data 

Sheets. Most likely, the person doing so is engaged in theft of intellectual property. 

• Microchip is willing to work with the customer who is concerned about the integrity of their code. 

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not 

mean that we are guaranteeing the product as “unbreakable.” 

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our 

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts 

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. 

Information contained in this publication regarding device 

applications and the like is provided only for your convenience 

and may be superseded by updates. It is your responsibility to 

ensure that your application meets with your specifications. 

MICROCHIP MAKES NO REPRESENTATIONS OR 

WARRANTIES OF ANY KIND WHETHER EXPRESS OR 

IMPLIED, WRITTEN OR ORAL, STATUTORY OR 

OTHERWISE, RELATED TO THE INFORMATION, 

INCLUDING BUT NOT LIMITED TO ITS CONDITION, 

QUALITY, PERFORMANCE, MERCHANTABILITY OR 

FITNESS FOR PURPOSE. Microchip disclaims all liability 

arising from this information and its use. Use of Microchip 

devices in life support and/or safety applications is entirely at 

the buyer’s risk, and the buyer agrees to defend, indemnify and 

hold harmless Microchip from any and all damages, claims, 

suits, or expenses resulting from such use. No licenses are 

conveyed, implicitly or otherwise, under any Microchip 

intellectual property rights. 

Trademarks 

The Microchip name and logo, the Microchip logo, dsPIC, 

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, 

PIC 32 logo, rfPIC and UNI/O are registered trademarks of 

Microchip Technology Incorporated in the U.S.A. and other 

countries. 

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, 

MXDEV, MXLAB, SEEVAL and The Embedded Control 

Solutions Company are registered trademarks of Microchip 

Technology Incorporated in the U.S.A. 

Analog-for-the-Digital Age, Application Maestro, chipKIT, 

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, 

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, 

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, 

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, 

MPLINK, mTouch, Omniscient Code Generation, PICC, 

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, 

rfLAB, Select Mode, Total Endurance, TSHARC, 

UniWinDriver, WiperLock and ZENA are trademarks of 

Microchip Technology Incorporated in the U.S.A. and other 

countries. 

SQTP is a service mark of Microchip Technology Incorporated 

in the U.S.A. 

All other trademarks mentioned herein are property of their 

respective companies. 

© 2012, Microchip Technology Incorporated, Printed in the 

U.S.A., All Rights Reserved. 

Printed on recycled paper. 

QUALITY MANAGEMENT SYSTEM 

CERTIFIED BY DNV 

== ISO/TS 16949 == 

ISBN: 978-1-62076-209-7 

Microchip received ISO/TS-16949:2009 certification for its worldwide 

headquarters, design and wafer fabrication facilities in Chandler and 

Tempe, Arizona; Gresham, Oregon and design centers in California 

and India. The Company’s quality system processes and procedures 

are for its PIC ® MCUs and dsPIC ® DSCs, KEELOQ ® code hopping 

devices, Serial EEPROMs, microperipherals, nonvolatile memory and 

analog products. In addition, Microchip’s quality system for the design 

and manufacture of development systems is ISO 9001:2000 certified. 


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11/29/11

PIC24FJ128GA310 Family Errata - Microchip

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