PIC24FJ128GA310 Family Errata - Microchip
PIC24FJ128GA310 Family Errata - Microchip
PIC24FJ128GA310 Family Errata - Microchip
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<strong>PIC24FJ128GA310</strong> FAMILY<br />
<strong>PIC24FJ128GA310</strong> <strong>Family</strong><br />
Silicon <strong>Errata</strong> and Data Sheet Clarification<br />
The <strong>PIC24FJ128GA310</strong> <strong>Family</strong> devices that you have<br />
received conform functionally to the current Device Data<br />
Sheet (DS39996F), except for the anomalies described<br />
in this document.<br />
The silicon issues discussed in the following pages are<br />
for silicon revisions with the Device and Revision IDs<br />
listed in Table 1. The silicon issues are summarized in<br />
Table 2.<br />
The errata described in this document will be addressed<br />
in future revisions of the <strong>PIC24FJ128GA310</strong> <strong>Family</strong><br />
silicon.<br />
Note:<br />
This document summarizes all silicon<br />
errata issues from all revisions of silicon,<br />
previous as well as current. Only the<br />
issues indicated in the last column of<br />
Table 2 apply to the current silicon<br />
revision (B2).<br />
Data Sheet clarifications and corrections start on page 5,<br />
following the discussion of silicon issues.<br />
The silicon revision level can be identified using the<br />
current version of MPLAB ® IDE and <strong>Microchip</strong>’s<br />
programmers, debuggers, and emulation tools, which<br />
are available at the <strong>Microchip</strong> corporate web site<br />
(www.microchip.com).<br />
For example, to identify the silicon revision level using<br />
MPLAB IDE in conjunction with MPLAB ICD 2 or<br />
PICkit 3:<br />
1. Using the appropriate interface, connect the<br />
device to the MPLAB ICD 2 programmer/<br />
debugger or PICkit 3.<br />
2. From the main menu in MPLAB IDE, select<br />
Configure>Select Device, and then select the<br />
target part number in the dialog box.<br />
3. Select the MPLAB hardware tool<br />
(Debugger>Select Tool).<br />
4. Perform a “Connect” operation to the device<br />
(Debugger>Connect). Depending on the development<br />
tool used, the part number and Device<br />
Revision ID value appear in the Output window.<br />
Note:<br />
If you are unable to extract the silicon<br />
revision level, please contact your local<br />
<strong>Microchip</strong> sales office for assistance.<br />
The DEVREV values for the various<br />
<strong>PIC24FJ128GA310</strong> <strong>Family</strong> silicon revisions are shown<br />
in Table 1.<br />
TABLE 1:<br />
SILICON DEVREV VALUES<br />
Part Number Device ID (1) Revision (2)<br />
Revision ID for Silicon<br />
PIC24FJ64GA306<br />
46C0h<br />
PIC24FJ64GA308<br />
46C4h<br />
PIC24FJ64GA310<br />
46C8h<br />
PIC24FJ128GA306<br />
46C2h<br />
4<br />
PIC24FJ128GA308<br />
46C6h<br />
<strong>PIC24FJ128GA310</strong><br />
46CAh<br />
Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration<br />
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.<br />
2: Refer to the “PIC24FJXXXDA1/DA2/GB2 Families Flash Programming Specification” (DS39970) for<br />
detailed information on Device and Revision IDs for your specific device.<br />
B2<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 1
<strong>PIC24FJ128GA310</strong> FAMILY<br />
TABLE 2:<br />
Module<br />
A/D Conversion<br />
During Sleep<br />
A/D Auto-Scan<br />
Mode<br />
SILICON ISSUE SUMMARY<br />
Feature<br />
Threshold<br />
Detect<br />
A/D Threshold<br />
Detect<br />
Item<br />
Number<br />
Issue Summary<br />
1. Auto-scan feature may not trigger correctly in Sleep<br />
mode.<br />
2. In Auto-scan mode, the highest number A/D channel<br />
may not cause interrupt.<br />
Affected<br />
Revisions (1)<br />
A/D A/D Accuracy 3. Noise injection on A/D input pin during A/D operation X<br />
(when reading a high-impedance input).<br />
VBTBOR VBAT BOR 4. VBTBOR (CW3) is not functional. X<br />
RTCC RTCC Operation 5. During a Power on Reset, the RTCC may be enabled. X<br />
A/D DNL 6. DNL will not meet data sheet specifications and possible X<br />
missing codes.<br />
Deep Sleep IPD 7. IPD maximum numbers will be higher than in the data X<br />
sheet.<br />
A/D DMA PIA Mode 8. DMA with A/D in PIA mode will not work X<br />
Reset<br />
Low-Voltage/ 9. POR and BOR bits will get set after Reset.<br />
Retention Sleep<br />
Note 1: Only those issues indicated in the last column apply to the current silicon revision.<br />
B2<br />
X<br />
X<br />
DS80532B-page 2<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
Silicon <strong>Errata</strong> Issues<br />
Note:<br />
1. Module: A/D Conversion During Sleep<br />
When the auto-scan feature of the Threshold<br />
Detect is enabled (AD1CON5 = 1), automatic<br />
scan may fail when these conditions occur<br />
together:<br />
• The Device is in Sleep mode, and<br />
• Timer1 is selected as the sample trigger clock<br />
source (AD1CON1 = 0110).<br />
Timer1 and other timers will function correctly as<br />
sample triggers in other power-saving modes,<br />
such as Idle mode.<br />
Work around<br />
Use INT0 to trigger the A/D in Sleep mode.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
2. Module: A/D Auto-Scan Mode<br />
In Auto-Scan mode (AD1CON5 = 1), when<br />
the Auto-Scan Interrupt mode bits are set to ‘11’<br />
(AD1CON5 = 11), the highest number channel<br />
selected for scanning in AD1CSSL, or<br />
AD1CSSH, may not trigger an interrupt on a valid<br />
comparison.<br />
Work around<br />
Add a dummy channel to the scanning sequence.<br />
For example, when scanning AN0 and AN1, set<br />
AD1CSSL to 0x0007 or 0x8003, or whatever is<br />
practical given the implementation.<br />
Also, if the highest number channel needs to be<br />
scanned, the AD1CHITH bit can be polled to<br />
observe a valid comparison.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
Corrections are shown in bold. Where<br />
possible, the original bold text formatting.<br />
3. Module: A/D Accuracy<br />
Noise injection on the A/D input pin during A/D<br />
operation (when reading a high-impedance input).<br />
Work around<br />
Increase the sample time for the channel that is<br />
being converted or reduce the source impedance.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
4. Module: VBTBOR<br />
VBTBOR (CW3) is not functional.<br />
Work around<br />
None.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
5. Module: RTCC<br />
During a Power-on Reset, the RTCC may be<br />
enabled.<br />
Work around<br />
To ensure that the RTCC is not enabled, make<br />
sure to clear the RTCEN after a POR. This is<br />
recommended whether RTCC is used or not.<br />
After a POR, execute the code below to disable<br />
the RTCC:<br />
MOV #NVMKEY,W1 ;move the address of<br />
NVMKEY into W1<br />
MOV #0x55, W2<br />
MOV W2, [W1] ;start 55/AA sequence<br />
MOV #0xAA, W3<br />
MOV W3, [W1]<br />
BSET RCFGCAL,#13 ;set the RTCWREN bit<br />
RCFGCALbits.RTCEN=0;<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 3
<strong>PIC24FJ128GA310</strong> FAMILY<br />
6. Module: A/D<br />
The DNL will not meet the data sheet<br />
specification; the DNL will be 1.5. There may be<br />
possible missing codes in 12-bit mode in<br />
locations: 511, 1023, 1535, 2047, 2559, 3071,<br />
3583.<br />
Work around<br />
None.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
7. Module: Deep Sleep<br />
The IPD maximum number for Deep Sleep may not<br />
meet the data sheet specification (DC70).<br />
The maximum values for Deep Sleep at 3.3V will<br />
be 2.5 µA.<br />
Work around<br />
None.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
8. Module: A/D<br />
The A/D will not work with DMA in PIA mode.<br />
Work around<br />
None.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
9. Module: Reset<br />
When the device is in Low-Voltage/Retention<br />
Sleep (Sleep with CW1 = 0 and RETEN = 1),<br />
if a Master Clear Reset is given, the POR<br />
(RCON) and BOR (RCON) bits will get set<br />
after the Reset.<br />
Work around<br />
Use registers, such as DSGPR0 or DSGPR1, to<br />
indicate the device was in Low-Voltage/Retention<br />
Sleep before the MCLR Reset is given.<br />
Affected Silicon Revisions<br />
B2<br />
X<br />
DS80532B-page 4<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
Data Sheet Clarifications<br />
The following typographic corrections and clarifications<br />
are to be noted for the latest version of the device data<br />
sheet (DS39996F):<br />
Note:<br />
Corrections are shown in bold. Where<br />
possible, the original bold text formatting<br />
has been removed for clarity.<br />
1. Module: Real Time Clock and Calendar<br />
In the data sheet, the beginning chapter note for<br />
Section 22.0 is corrected as follows:<br />
Note:<br />
This data sheet summarizes the features<br />
of this group of PIC24F devices. It is not<br />
intended to be a comprehensive reference<br />
source. For more information on the<br />
Real-Time Clock and Calendar, refer to<br />
the “PIC24F <strong>Family</strong> Reference Manual”,<br />
Section 56. RTCC with External<br />
Power Control (RTCC) (DS39745).<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 5
<strong>PIC24FJ128GA310</strong> FAMILY<br />
2. Module: Special Features<br />
On Page 342, in Register 29-5: DEVID: Device<br />
ID Register, the contents of the bits are<br />
changed as shown below in bold:<br />
REGISTER 29-5:<br />
DEVID: DEVICE ID REGISTER<br />
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1<br />
— — — — — — — —<br />
bit 23 bit 16<br />
R R R R R R R R<br />
FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0<br />
bit 15 bit 8<br />
R R R R R R R R<br />
DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0<br />
bit 7 bit 0<br />
Legend: R = Readable bit U = Unimplemented bit<br />
bit 23-16 Unimplemented: Read as ‘1’<br />
bit 15-8 FAMID: Device <strong>Family</strong> Identifier bits<br />
0100 0110 = <strong>PIC24FJ128GA310</strong> <strong>Family</strong><br />
bit 7-0 DEV: Individual Device Identifier bits<br />
1100 0000 = PIC24FJ64GA306<br />
1100 0010 = PIC24FJ128GA306<br />
1100 0100 = PIC24FJ64GA308<br />
1100 0110 = PIC24FJ128GA308<br />
1100 1000 = PIC24FJ64GA310<br />
1100 1010 = <strong>PIC24FJ128GA310</strong><br />
DS80532B-page 6<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
3. Module: Special Features<br />
On page 336, in Register 29-2: CW2: Flash<br />
Configuration Word 2, a new bit has been added<br />
for CW2, BOREN1, as shown below in bold:<br />
REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2<br />
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1<br />
— — — — — — — —<br />
bit 23 bit 16<br />
R/PO-1 r-1 r-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1<br />
IESO r r ALTVRF1 ALTVRF0 FNOSC2 FNOSC1 FNOSC0<br />
bit 15 bit 8<br />
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1<br />
FCKSM1 FCKSM0 OSCIOFCN IOL1WAY BOREN1 r POSCMD1 POSCMD0<br />
bit 7 bit 0<br />
Legend:<br />
r = Reserved bit<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 23-16 Unimplemented: Read as ‘1’<br />
bit 15 IESO: Internal External Switchover bit<br />
1 = IESO mode (Two-Speed Start-up) is enabled<br />
0 = IESO mode (Two-Speed Start-up) is disabled<br />
bit 14-13 Reserved: Always maintain as ‘1’<br />
bit 12-11 ALTVRF: Alternate VREF/CVREF Pins Selection bits<br />
00 = Voltage reference input, A/D = RB0/RB1, Comparator = RB0/RB1<br />
01 = Voltage reference input, A/D = RB0/RB1, Comparator = RA9, RA10<br />
10 = Voltage reference input, A/D = RA9/RA10, Comparator = RB0, RB1<br />
11 = Voltage reference input, A/D = RA9/RA10, Comparator = RA9, RA10<br />
bit 10-8 FNOSC: Initial Oscillator Select bits<br />
111 = Fast RC Oscillator with Postscaler (FRCDIV)<br />
110 = Reserved<br />
101 = Low-Power RC Oscillator (LPRC)<br />
100 = Secondary Oscillator (SOSC)<br />
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)<br />
010 = Primary Oscillator (XT, HS, EC)<br />
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)<br />
000 = Fast RC Oscillator (FRC)<br />
bit 7-6 FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits<br />
1x = Clock switching and Fail-Safe Clock Monitor are disabled<br />
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled<br />
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled<br />
bit 5 OSCIOFCN: OSCO Pin Configuration bit<br />
If POSCMD = 11 or 00:<br />
1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)<br />
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)<br />
If POSCMD = 10 or 01:<br />
OSCIOFCN has no effect on OSCO/CLKO/RC15.<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 7
<strong>PIC24FJ128GA310</strong> FAMILY<br />
REGISTER 29-2:<br />
CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)<br />
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit<br />
1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been<br />
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.<br />
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been<br />
completed<br />
bit 3 BOREN1: BOR Override bit<br />
This bit should be set/cleared based on the BOREN (CW3) setting<br />
1 = BOR is enabled (CW3, BOREN = 1)<br />
0 = BOR is disabled (CW3 , BOREN = 0)<br />
Allowed combinations are shown below:<br />
BOREN (CW3): BOREN1 (CW2)<br />
11 = BOR is enabled<br />
10 = Reserved<br />
01 = Reserved<br />
00 = BOR is disabled<br />
bit 2 Reserved: Always maintain as ‘1’<br />
bit 1-0 POSCMD: Primary Oscillator Configuration bits<br />
11 = Primary Oscillator mode is disabled<br />
10 = HS Oscillator mode is selected<br />
01 = XT Oscillator mode is selected<br />
00 = EC Oscillator mode is selected<br />
DS80532B-page 8<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
4. Module: Special Features<br />
On Page 338, in Register 29-3: CW3: Flash<br />
Configuration Word 3, bit 12 has been modified<br />
as shown below in bold:<br />
REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3<br />
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1<br />
— — — — — — — —<br />
bit 23 bit 16<br />
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1<br />
WPEND WPCFG WPDIS BOREN WDTWIN1 WDTWIN0 r SOSCSEL<br />
bit 15 bit 8<br />
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1<br />
VBTBOR WPFP6 (3) WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0<br />
bit 7 bit 0<br />
Legend: PO = Program Once bit r = Reserved bit<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 23-16 Unimplemented: Read as ‘1’<br />
bit 15 WPEND: Segment Write Protection End Page Select bit<br />
1 = Protected code segment upper boundary is at the last page of program memory; the lower<br />
boundary is the code page specified by WPFP<br />
0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper<br />
boundary is the code page specified by WPFP<br />
bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit<br />
1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected (1)<br />
0 = Last page and Flash Configuration Words are write-protected provided WPDIS = ‘0’<br />
bit 13 WPDIS: Segment Write Protection Disable bit<br />
1 = Segmented code protection is disabled<br />
0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and<br />
WPFPx Configuration bits<br />
bit 12 BOREN: Brown-out Reset Enable bit (also see CW2 BOREN1)<br />
1 = BOR is enabled (all modes except Deep Sleep) (BOREN1 = 1)<br />
0 = BOR is disabled (BOREN1 = 0)<br />
Allowed combinations are shown below:<br />
BOREN (CW3): BOREN1 (CW2)<br />
11 = BOR is enabled<br />
10 = Reserved<br />
01 = Reserved<br />
00 = BOR is disabled<br />
Note 1: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word page, the<br />
Configuration Word page is protected.<br />
2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1).<br />
3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be<br />
maintained as ‘0’.<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 9
<strong>PIC24FJ128GA310</strong> FAMILY<br />
REGISTER 29-3:<br />
CW3: FLASH CONFIGURATION WORD 3 (CONTINUED)<br />
bit 11-10 WDTWIN: Watchdog Timer Window Width Select bits<br />
11 =25%<br />
10 =37.5%<br />
01 =50%<br />
00 =75%<br />
bit 9 Reserved: Always maintain as ‘1’<br />
bit 8<br />
SOSCSEL: SOSC Selection bit<br />
1 = SOSC circuit is selected<br />
0 = Digital (SCLKI) mode (2)<br />
bit 7 VBTBOR: VBAT BOR Enable bit<br />
1 = VBAT BOR is enabled<br />
0 = VBAT BOR is disabled<br />
bit 6-0 WPFP: Write-Protected Code Segment Boundary Page bits (3)<br />
Designates the 256 instruction words page boundary of the protected code segment.<br />
If WPEND = 1:<br />
Specifies the lower page boundary of the code-protected segment; the last page being the last<br />
implemented page in the device.<br />
If WPEND = 0:<br />
Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary.<br />
Note 1: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word page, the<br />
Configuration Word page is protected.<br />
2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1).<br />
3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be<br />
maintained as ‘0’.<br />
5. Module: Timer 1<br />
On Page 197, the first paragraph has been<br />
changed as shown below:<br />
The Timer1 module is a 16-bit timer that can<br />
operate as a free-running, interval timer/counter.<br />
Timer1 can operate in three modes:<br />
6. Module: Pin Diagrams<br />
On page 3, 4 and 5, the note “Pinouts are<br />
subject to change” has been removed.<br />
7. Module: Pin Diagrams<br />
The T1CK has been removed from RB9 ports<br />
from all the following pinouts:<br />
Page 3, on 64-pin devices, the Pin 22 has been<br />
modified to remove T1CK as AN9/RP9/SEG30/<br />
COM6/PMA7/CN27/RB9.<br />
Page 4, on 80-pin devices, the Pin 28 has been<br />
modified to remove T1CK as AN9/RP9/SEG30/<br />
COM6/CN27/RB9.<br />
Page 5, on 100-pin devices, the Pin 33 has been<br />
modified to remove T1CK as AN9/RP9/SEG30/<br />
COM6/CN27/RB9.<br />
Page 8, on Table 1, Pin L4 has been modified to<br />
remove T1CK as AN9/RP9/COM6/SEG30/<br />
CN27/RB9.<br />
8. Module: Guidelines for Getting Started<br />
with 16-Bit Microcontrollers<br />
Page 27, Table 1-4, the T1CK has been<br />
removed.<br />
DS80532B-page 10<br />
2012 <strong>Microchip</strong> Technology Inc.
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 11<br />
9. Module: Memory Organization<br />
On page 57, Table 4-22, ANSA10 and ANSA9 are added in bold as<br />
shown below:<br />
TABLE 4-22:<br />
ANALOG CONFIGURATION REGISTER MAP<br />
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0<br />
ANCFG 04DE — — — — — — — — — — — — — VBG6EN VBG2EN VBGEN 0000<br />
ANSA 04E0 — — — — — ANSA10 ANSA9 — ANSA7 (1) ANSA6 (1) — — — — — — 06C0<br />
ANSB 04E2 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 FFFF<br />
ANSC 04E4 — — — — — — — — — — — ANSC4 (1) — — — — 0010<br />
ANSD 04E6 — — — — ANSD11 ANSD10 — — ANSD7 ANSD6 — — — — — — 0CC0<br />
ANSE 04E8 — — — — — — ANSE9 (2) — ANSE7 ANSE6 ANSE5 ANSE4 — — — — 02F0<br />
ANSG 04EC — — — — — — ANSG9 ANSG8 ANSG7 ANSG6 — — — — — — 03C0<br />
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.<br />
Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.<br />
2: These bits are unimplemented in 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital functionality on RE9.<br />
All<br />
Resets<br />
<strong>PIC24FJ128GA310</strong> FAMILY
<strong>PIC24FJ128GA310</strong> FAMILY<br />
10. Module: I/O Ports<br />
On page 169, Register 11-1, ANSA10 and<br />
ANSA9 are added in bold as shown below:<br />
REGISTER 11-1:<br />
ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER<br />
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 U-0<br />
— — — — — ANSA10 ANSA9 —<br />
bit 15 bit 8<br />
R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0<br />
ANSA7 (1) ANSA6 (1) — — — — — —<br />
bit 7 bit 0<br />
Legend:<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 15-11 Unimplemented: Read as ‘0’<br />
bit 10-9 ANSA: Analog Function Selection bits (1)<br />
1 = Pin is configured in Analog mode; I/O port read is disabled<br />
0 = Pin is configured in Digital mode; I/O port read is enabled<br />
bit 8 Unimplemented: Read as ‘0’<br />
bit 7-6 ANSA: Analog Function Selection bits (1)<br />
1 = Pin is configured in Analog mode; I/O port read is disabled<br />
0 = Pin is configured in Digital mode; I/O port read is enabled<br />
bit 5-0 Unimplemented: Read as ‘0’<br />
Note 1:<br />
These bits are not available in 64-pin and 80-pin devices.<br />
DS80532B-page 12<br />
2012 <strong>Microchip</strong> Technology Inc.
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 13<br />
11. Module: Memory Organization<br />
On Page 63, Table 4-31, LVDCON has changed to HLVDCON, as shown<br />
in bold below:<br />
TABLE 4-31:<br />
SYSTEM CONTROL (CLOCK AND RESET) REGISTER MAP<br />
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0<br />
RCON 0740 TRAPR IOPUWR — RETEN — DPSLP CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1<br />
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note 2<br />
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 0100<br />
OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000<br />
REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000<br />
HLVDCON 0756 LVDEN — LSIDL — — — — — DIR BGVST IRVST — LVDL3 LVDL2 LVDL1 LVDL0 0000<br />
RCON2 0762 — — — — — — — — — — — r VDDBOR VDDPOR VBPOR VBAT Note 1<br />
Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal.<br />
Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section 7.0 “Resets” for more information.<br />
2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 9.0 “Oscillator Configuration” for more information.<br />
All<br />
Resets<br />
<strong>PIC24FJ128GA310</strong> FAMILY
<strong>PIC24FJ128GA310</strong> FAMILY<br />
12. Module: I/O Ports<br />
On Page 184, Register 11-20, SPI2 has<br />
changed to SPI1, as shown in bold below:<br />
REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20<br />
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1<br />
— — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0<br />
bit 15 bit 8<br />
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1<br />
— — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0<br />
bit 7 bit 0<br />
Legend:<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 15-14 Unimplemented: Read as ‘0’<br />
bit 13-8 SCK1R: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits<br />
bit 7-6 Unimplemented: Read as ‘0’<br />
bit 5-0 SDI1R: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits<br />
On Page 185, Register 11-22, T1CKx has changed to<br />
SCKRx, as shown in bold below:<br />
REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22<br />
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1<br />
— — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0<br />
bit 15 bit 8<br />
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1<br />
— — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0<br />
bit 7 bit 0<br />
Legend:<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 15-14 Unimplemented: Read as ‘0’<br />
bit 13-8 SCK2R: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits<br />
bit 7-6 Unimplemented: Read as ‘0’<br />
bit 5-0 SDI2R: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits<br />
DS80532B-page 14<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
13. Module: Electrical Characteristics<br />
On Page 370, Table 32-19, the FOSC parameter<br />
for the oscillator min. frequency changed<br />
(OS10), as shown in bold below:<br />
TABLE 32-19:<br />
AC CHARACTERISTICS<br />
EXTERNAL CLOCK TIMING REQUIREMENTS<br />
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)<br />
Operating temperature-40°C £ TA £ +85°C for Industrial<br />
Param<br />
No.<br />
Symbol Characteristic Min Typ (1) Max Units Conditions<br />
OS10 FOSC External CLKI Frequency<br />
(External clocks allowed<br />
only in EC mode)<br />
DC<br />
4<br />
Oscillator Frequency 3.5<br />
4<br />
10<br />
4<br />
31<br />
—<br />
—<br />
—<br />
—<br />
—<br />
—<br />
—<br />
32<br />
8<br />
10<br />
8<br />
32<br />
8<br />
33<br />
MHz<br />
MHz<br />
MHz<br />
MHz<br />
MHz<br />
MHz<br />
kHz<br />
EC<br />
ECPLL<br />
XT<br />
XTPLL<br />
HS<br />
HSPLL<br />
SOSC<br />
OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for<br />
FOSC value<br />
OS25 TCY Instruction Cycle Time (2) 62.5 — DC ns<br />
OS30<br />
OS31<br />
TosL,<br />
TosH<br />
TosR,<br />
TosF<br />
External Clock in (OSCI)<br />
High or Low Time<br />
External Clock in (OSCI)<br />
Rise or Fall Time<br />
0.45 x TOSC — — ns EC<br />
— — 20 ns EC<br />
OS40 TckR CLKO Rise Time (3) — 6 10 ns<br />
OS41 TckF CLKO Fall Time (3) — 6 10 ns<br />
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only<br />
and are not tested.<br />
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are<br />
based on characterization data for that particular oscillator type, under standard operating conditions, with<br />
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation<br />
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an<br />
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time<br />
limit is “DC” (no clock) for all devices.<br />
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the<br />
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 15
<strong>PIC24FJ128GA310</strong> FAMILY<br />
14. Module: Electrical Characteristics<br />
On Page 360, the text in Figure 32-1 has been<br />
modified to PIC24FJXXXGA3XX, as shown in<br />
bold below:<br />
FIGURE 32-1:<br />
<strong>PIC24FJ128GA310</strong> FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)<br />
3.6V 3.6V<br />
PIC24FJXXXGA3XX<br />
Voltage (VDD)<br />
2.2V<br />
VBOR<br />
2.2V<br />
VBOR<br />
Frequency<br />
32 MHz<br />
Note:<br />
VCAP (nominal On-Chip Regulator output voltage) = 1.8V.<br />
15. Module: 12-Bit A/D Converter with<br />
Threshold Scan<br />
On Page 307, Register 24-7, the text has been<br />
modified, as shown in bold below:<br />
REGISTER 24-7:<br />
ANCFG: A/D BAND GAP REFERENCE CONFIGURATION<br />
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0<br />
— — — — — — — —<br />
bit 15 bit 8<br />
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0<br />
— — — — — VBG6EN VBG2EN VBGEN<br />
bit 7 bit 0<br />
Legend:<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 15-3 Unimplemented: Read as ‘0’<br />
bit 2<br />
bit 1<br />
bit 0<br />
VBG6EN: A/D Input VBG/6 Enable bit<br />
1 = Band gap voltage, divided by six reference (VBG/6), is enabled<br />
0 = Band gap, divided by six reference (VBG/6), is disabled<br />
VBG2EN: A/D Input VBG/2 Enable bit<br />
1 = Band gap voltage, divided by two reference (VBG/2), is enabled<br />
0 = Band gap, divided by two reference (VBG/2), is disabled<br />
VBGEN: A/D Input VBG Enable bit<br />
1 = Band gap voltage reference (VBG) is enabled<br />
0 = Band gap reference (VBG) is disabled<br />
DS80532B-page 16<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
16. Module: Real-Time Clock and Calendar<br />
(RTCC)<br />
On Page 276, in Section 22.1, a note has been<br />
added as shown in bold:<br />
22.1 RTCC Source Clock<br />
The user can select between the SOSC crystal<br />
oscillator, LPRC internal oscillator or an external<br />
50 Hz/60 Hz power line input as the clock reference<br />
for the RTCC module. This gives the user<br />
an option to trade off system cost, accuracy and<br />
power consumption, based on the overall system<br />
needs. If using SOSC for time-sensitive<br />
application, do not enable the LCD pin<br />
(SEG17) adjacent to the SOSCI pin.<br />
Note:<br />
Do not enable the LCD segment pin,<br />
SEG17 on RD0, if the SOSC is used for<br />
time-sensitive applications. Avoid<br />
high-frequency switching adjacent to<br />
the SOSCO and SOSCI pins.<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 17
<strong>PIC24FJ128GA310</strong> FAMILY<br />
17. Module: A/D Converter<br />
On Page 300, Register 24-1, the SSRC<br />
bits have one more mode (0110), as shown in<br />
bold text below:<br />
REGISTER 24-1: AD1CON1: A/D CONTROL REGISTER 1<br />
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0<br />
ADON — ADSIDL DMABM (1) DMAEN MODE12 FORM1 FORM0<br />
bit 15 bit 8<br />
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS<br />
SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE<br />
bit 7 bit 0<br />
Legend: U = Unimplemented bit, read as ‘0’<br />
R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 15 ADON: A/D Operating Mode bit<br />
1 = A/D Converter module is operating<br />
0 = A/D Converter is off<br />
bit 14 Unimplemented: Read as ‘0’<br />
bit 13 ADSIDL: Stop in Idle Mode bit<br />
1 = Discontinue module operation when device enters Idle mode<br />
0 = Continue module operation in Idle mode<br />
bit 12 DMABM: Extended DMA Buffer Mode Select bit(1)<br />
1 = Extended Buffer mode: Buffer address is defined by the DMAnDST register<br />
0 = PIA mode: Buffer addresses are defined by the DMA controller and AD1CON4<br />
bit 11 DMAEN: Extended DMA/Buffer Enable bit<br />
1 = Extended DMA and buffer features are enabled<br />
0 = Extended features are disabled<br />
bit 10 MODE12: 12-Bit Operation Mode bit<br />
1 = 12-bit A/D operation<br />
0 = 10-bit A/D operation<br />
bit 9-8 FORM: Data Output Format bits (see formats following)<br />
11 = Fractional result, signed, left-justified<br />
10 = Absolute fractional result, unsigned, left-justified<br />
01 = Decimal result, signed, right-justified<br />
00 = Absolute decimal result, unsigned, right-justified<br />
bit 7-4 SSRC: Sample Clock Source Select bits<br />
1xxx = Unimplemented, do not use<br />
0111 = Internal counter ends sampling and starts conversion (auto-convert). Do not use in<br />
Auto-Scan mode<br />
0110 = Timer1 in Sleep (for Auto-Scan mode)<br />
0101 =TMR1<br />
0100 =CTMU<br />
0011 =TMR5<br />
0010 =TMR3<br />
0001 =INT0<br />
0000 = The SAMP bit must be cleared by software to start conversion<br />
Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN = 1).<br />
DS80532B-page 18<br />
2012 <strong>Microchip</strong> Technology Inc.
<strong>PIC24FJ128GA310</strong> FAMILY<br />
REGISTER 24-1:<br />
AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED)<br />
bit 3 Unimplemented: Read as ‘0’<br />
bit 2 ASAM: A/D Sample Auto-Start bit<br />
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set<br />
0 = Sampling begins when SAMP bit is manually set<br />
bit 1 SAMP: A/D Sample Enable bit<br />
1 = A/D Sample-and-Hold amplifiers are sampling<br />
0 = A/D Sample-and-Hold amplifiers are holding<br />
bit 0 DONE: A/D Conversion Status bit<br />
1 = A/D conversion cycle has completed<br />
0 = A/D conversion has not started or is in progress<br />
Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN = 1).<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 19
<strong>PIC24FJ128GA310</strong> FAMILY<br />
APPENDIX A:<br />
DOCUMENT<br />
REVISION HISTORY<br />
Rev A Document (11/2011)<br />
Initial release of this document. Includes silicon issues 1<br />
(A/D Conversion During Sleep), 2 (A/D Auto-Scan<br />
Mode), 3 (A/D Accuracy), 4 (VBTBOR) and 5 (RTCC).<br />
Added data sheet clarification 1 (Section 22.0 Real<br />
Time Clock and Calendar).<br />
Rev B Document (4/2012)<br />
Included changes to silicon issue 1 (A/D Conversion<br />
During Sleep) and added silicon issues 8 (A/D) and<br />
9 (Reset), and added data sheet clarifications<br />
2 (Special Features), 3 (Special Features), 4 (Special<br />
Features), 5 (Timer1), 6 (Pin Diagrams), 7 (Pin Diagrams),<br />
8 (Guidelines for Getting Started with 16-Bit<br />
Microcontrollers), 9 (Memory Organization), 10 (I/O<br />
Ports), 11 (Memory Organization), 12 (I/O Ports),<br />
13 (Electrical Characteristics), 14 (Electrical Characteristics),<br />
15 (12-Bit A/D Converter with Threshold<br />
Scan), 16 (Real-Time Clock and Calendar – RTCC)<br />
and 17 (A/D Converter).<br />
DS80532B-page 20<br />
2012 <strong>Microchip</strong> Technology Inc.
Note the following details of the code protection feature on <strong>Microchip</strong> devices:<br />
• <strong>Microchip</strong> products meet the specification contained in their particular <strong>Microchip</strong> Data Sheet.<br />
• <strong>Microchip</strong> believes that its family of products is one of the most secure families of its kind on the market today, when used in the<br />
intended manner and under normal conditions.<br />
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our<br />
knowledge, require using the <strong>Microchip</strong> products in a manner outside the operating specifications contained in <strong>Microchip</strong>’s Data<br />
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.<br />
• <strong>Microchip</strong> is willing to work with the customer who is concerned about the integrity of their code.<br />
• Neither <strong>Microchip</strong> nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not<br />
mean that we are guaranteeing the product as “unbreakable.”<br />
Code protection is constantly evolving. We at <strong>Microchip</strong> are committed to continuously improving the code protection features of our<br />
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Information contained in this publication regarding device<br />
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MICROCHIP MAKES NO REPRESENTATIONS OR<br />
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The <strong>Microchip</strong> name and logo, the <strong>Microchip</strong> logo, dsPIC,<br />
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SQTP is a service mark of <strong>Microchip</strong> Technology Incorporated<br />
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All other trademarks mentioned herein are property of their<br />
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© 2012, <strong>Microchip</strong> Technology Incorporated, Printed in the<br />
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== ISO/TS 16949 ==<br />
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are for its PIC ® MCUs and dsPIC ® DSCs, KEELOQ ® code hopping<br />
devices, Serial EEPROMs, microperipherals, nonvolatile memory and<br />
analog products. In addition, <strong>Microchip</strong>’s quality system for the design<br />
and manufacture of development systems is ISO 9001:2000 certified.<br />
2012 <strong>Microchip</strong> Technology Inc. DS80532B-page 21
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Fax: 81-45-471-6122<br />
Korea - Daegu<br />
Tel: 82-53-744-4301<br />
Fax: 82-53-744-4302<br />
Korea - Seoul<br />
Tel: 82-2-554-7200<br />
Fax: 82-2-558-5932 or<br />
82-2-558-5934<br />
Malaysia - Kuala Lumpur<br />
Tel: 60-3-6201-9857<br />
Fax: 60-3-6201-9859<br />
Malaysia - Penang<br />
Tel: 60-4-227-8870<br />
Fax: 60-4-227-4068<br />
Philippines - Manila<br />
Tel: 63-2-634-9065<br />
Fax: 63-2-634-9069<br />
Singapore<br />
Tel: 65-6334-8870<br />
Fax: 65-6334-8850<br />
Taiwan - Hsin Chu<br />
Tel: 886-3-5778-366<br />
Fax: 886-3-5770-955<br />
Taiwan - Kaohsiung<br />
Tel: 886-7-536-4818<br />
Fax: 886-7-330-9305<br />
Taiwan - Taipei<br />
Tel: 886-2-2500-6610<br />
Fax: 886-2-2508-0102<br />
Thailand - Bangkok<br />
Tel: 66-2-694-1351<br />
Fax: 66-2-694-1350<br />
EUROPE<br />
Austria - Wels<br />
Tel: 43-7242-2244-39<br />
Fax: 43-7242-2244-393<br />
Denmark - Copenhagen<br />
Tel: 45-4450-2828<br />
Fax: 45-4485-2829<br />
France - Paris<br />
Tel: 33-1-69-53-63-20<br />
Fax: 33-1-69-30-90-79<br />
Germany - Munich<br />
Tel: 49-89-627-144-0<br />
Fax: 49-89-627-144-44<br />
Italy - Milan<br />
Tel: 39-0331-742611<br />
Fax: 39-0331-466781<br />
Netherlands - Drunen<br />
Tel: 31-416-690399<br />
Fax: 31-416-690340<br />
Spain - Madrid<br />
Tel: 34-91-708-08-90<br />
Fax: 34-91-708-08-91<br />
UK - Wokingham<br />
Tel: 44-118-921-5869<br />
Fax: 44-118-921-5820<br />
China - Zhuhai<br />
Tel: 86-756-3210040<br />
Fax: 86-756-3210049<br />
11/29/11<br />
DS80532B-page 22<br />
2012 <strong>Microchip</strong> Technology Inc.