xmega a3u - Elfa
xmega a3u - Elfa
xmega a3u - Elfa
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XMEGA A3U<br />
36.15 SPI Characteristics<br />
Figure 36-5.<br />
SPI timing requirements in master mode.<br />
SS<br />
tMOS<br />
tSCKR<br />
tSCKF<br />
SCK<br />
(CPOL = 0)<br />
SCK<br />
(CPOL = 1)<br />
tSCKW<br />
tSCKW<br />
tMIS<br />
tMIH<br />
tSCK<br />
MISO<br />
(Data Input)<br />
MSB<br />
LSB<br />
tMOH<br />
tMOH<br />
MOSI<br />
(Data Output)<br />
MSB<br />
LSB<br />
Figure 36-6.<br />
SPI timing requirements in slave mode.<br />
SS<br />
tSSS<br />
tSCKR<br />
tSCKF<br />
tSSH<br />
SCK<br />
(CPOL = 0)<br />
SCK<br />
(CPOL = 1)<br />
tSSCKW<br />
tSSCKW<br />
tSIS<br />
tSIH<br />
tSSCK<br />
MOSI<br />
(Data Input)<br />
MSB<br />
LSB<br />
tSOSSS<br />
tSOS<br />
tSOSSH<br />
MISO<br />
(Data Output)<br />
MSB<br />
LSB<br />
8386B–AVR–12/11<br />
88
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