xmega a3u - Elfa

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XMEGA A3U 31. Programming and Debugging 31.1 Features • Programming – External programming through PDI or JTAG interfaces Minimal protocol overhead for fast operation Built-in error detection and handling for reliable operation – Boot loader support for programming through any communication interface • Debugging – Nonintrusive, real-time, on-chip debug system – No software or hardware resources required from device except pin connection – Program flow control Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor – Unlimited number of user program breakpoints – Unlimited number of user data breakpoints, break on: Data location read, write, or both read and write Data location content equal or not equal to a value Data location content is greater or smaller than a value Data location content is within or outside a range – No limitation on device clock frequency • Program and Debug Interface (PDI) – Two-pin interface for external programming and debugging – Uses the Reset pin and a dedicated pin – No I/O pins required during programming or debugging • JTAG interface – Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging – Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG) 31.2 Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer, which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std. 1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical layer. 8386B–AVR–12/11 56
XMEGA A3U 32. Pinout and Pin Functions The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 32.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 32.1.1 Operation/Power Supply V CC AV CC GND Digital supply voltage Analog supply voltage Ground 32.1.2 Port Interrupt functions SYNC ASYNC Port pin with full synchronous and limited asynchronous interrupt function Port pin with full synchronous and full asynchronous interrupt function 32.1.3 Analog functions ACn ACnOUT ADCn DACn A REF Analog Comparator input pin n Analog Comparator n Output Analog to Digital Converter input pin n Digital to Analog Converter output pin n Analog Reference input pin 32.1.4 Timer/Counter and AWEX functions OCnxLS OCnxHS Output Compare Channel x Low Side for Timer/Counter n Output Compare Channel x High Side for Timer/Counter n 8386B–AVR–12/11 57
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Features • High-performance, low-
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XMEGA A3U 2. Pinout/Block Diagram F
Page 5 and 6: XMEGA A3U 3.1 Block Diagram All Atm
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29 and 30: XMEGA A3U Table 14-1. Reset and int
Page 31 and 32: XMEGA A3U 15.3 Output Driver All po
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39 and 40: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 41 and 42: XMEGA A3U the configuration of thes
Page 43 and 44: XMEGA A3U It is possible to disable
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51 and 52: XMEGA A3U Both internal and externa
Page 53 and 54: XMEGA A3U The DAC has high drive st
Page 55: XMEGA A3U Figure 30-1. Analog compa
Page 59 and 60: XMEGA A3U 32.2 Alternate Pin Functi
Page 61 and 62: XMEGA A3U Table 32-6. Port F - alte
Page 63 and 64: XMEGA A3U Base address Name Descrip
Page 65 and 66: XMEGA A3U Mnemonics Operands Descri
Page 67 and 68: XMEGA A3U Mnemonics Operands Descri
Page 69 and 70: XMEGA A3U 35.2 64M2 D Marked Pin# 1
Page 71 and 72: XMEGA A3U Table 36-3. Operating vol
Page 73 and 74: XMEGA A3U Table 36-5. Current consu
Page 75 and 76: XMEGA A3U 36.5 I/O Pin Characterist
Page 77 and 78: XMEGA A3U Table 36-10. Accuracy cha
Page 79 and 80: XMEGA A3U Table 36-14. Gain error A
Page 81 and 82: XMEGA A3U 36.13 Flash and EEPROM Me
Page 83 and 84: XMEGA A3U 36.14.6 External clock ch
Page 85 and 86: XMEGA A3U 36.14.7 External 16MHz cr
Page 87 and 88: XMEGA A3U 36.14.8 External 32.768kH
Page 89 and 90: XMEGA A3U Table 36-31. SPI timing c
Page 91 and 92: XMEGA A3U Table 36-32. t HD;STA t L
Page 93 and 94: XMEGA A3U Figure 37-3. Active mode
Page 95 and 96: XMEGA A3U Figure 37-7. Active mode
Page 97 and 98: XMEGA A3U Figure 37-11. Idle mode s
Page 99 and 100: XMEGA A3U 37.1.3 Power-down mode su
Page 101 and 102: XMEGA A3U Figure 37-19. Standby sup
Page 103 and 104: XMEGA A3U 37.2.2 Output Voltage vs.
Page 105 and 106: XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
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XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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xmega a3u - Elfa

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