xmega a3u - Elfa

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XMEGA A3U 29. DAC – 12-bit Digital to Analog Converter 29.1 Features • One Digital to Analog Converter (DAC) • 12-bit resolution • Two independent, continuous-drive output channels • Up to one million samples per second conversion rate per DAC channel • Built-in calibration that removes: – Offset error – Gain error • Multiple conversion trigger sources – On new available data – Events from the event system • High drive capabilities and support for – Resistive loads – Capacitive loads – Combined resistive and capacitive loads • Internal and external reference options • DAC output available as input to analog comparator and ADC • Low-power mode, with reduced drive strength • Optional DMA transfer of data 29.2 Overview The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in calibration system can remove offset and gain error when loaded with calibration values from software. Figure 29-1. DAC overview. DMA req (Data Empty) CH0DATA 12 D A T A DAC0 Output Driver AVCC Internal 1.00V AREFA AREFB Reference selection Trigger CTRLB Trigger Select Select Enable CTRLA Enable Internal Output enable Int. driver To AC/ADC DMA req (Data Empty) CH1DATA 12 D A T A DAC1 Output Driver A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC. 52 8386B–AVR–12/11
XMEGA A3U The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or ADC. PORTB has one DAC. Notation of this peripheral is DACB. 8386B–AVR–12/11 53
Page 1 and 2: Features • High-performance, low-
Page 3 and 4: XMEGA A3U 2. Pinout/Block Diagram F
Page 5 and 6: XMEGA A3U 3.1 Block Diagram All Atm
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29 and 30: XMEGA A3U Table 14-1. Reset and int
Page 31 and 32: XMEGA A3U 15.3 Output Driver All po
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39 and 40: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 41 and 42: XMEGA A3U the configuration of thes
Page 43 and 44: XMEGA A3U It is possible to disable
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51: XMEGA A3U Both internal and externa
Page 55 and 56: XMEGA A3U Figure 30-1. Analog compa
Page 57 and 58: XMEGA A3U 32. Pinout and Pin Functi
Page 59 and 60: XMEGA A3U 32.2 Alternate Pin Functi
Page 61 and 62: XMEGA A3U Table 32-6. Port F - alte
Page 63 and 64: XMEGA A3U Base address Name Descrip
Page 65 and 66: XMEGA A3U Mnemonics Operands Descri
Page 67 and 68: XMEGA A3U Mnemonics Operands Descri
Page 69 and 70: XMEGA A3U 35.2 64M2 D Marked Pin# 1
Page 71 and 72: XMEGA A3U Table 36-3. Operating vol
Page 73 and 74: XMEGA A3U Table 36-5. Current consu
Page 75 and 76: XMEGA A3U 36.5 I/O Pin Characterist
Page 77 and 78: XMEGA A3U Table 36-10. Accuracy cha
Page 79 and 80: XMEGA A3U Table 36-14. Gain error A
Page 81 and 82: XMEGA A3U 36.13 Flash and EEPROM Me
Page 83 and 84: XMEGA A3U 36.14.6 External clock ch
Page 85 and 86: XMEGA A3U 36.14.7 External 16MHz cr
Page 87 and 88: XMEGA A3U 36.14.8 External 32.768kH
Page 89 and 90: XMEGA A3U Table 36-31. SPI timing c
Page 91 and 92: XMEGA A3U Table 36-32. t HD;STA t L
Page 93 and 94: XMEGA A3U Figure 37-3. Active mode
Page 95 and 96: XMEGA A3U Figure 37-7. Active mode
Page 97 and 98: XMEGA A3U Figure 37-11. Idle mode s
Page 99 and 100: XMEGA A3U 37.1.3 Power-down mode su
Page 101 and 102: XMEGA A3U Figure 37-19. Standby sup
Page 103 and 104:
XMEGA A3U 37.2.2 Output Voltage vs.
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XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
Page 115 and 116:
XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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