xmega a3u - Elfa

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XMEGA A3U 3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA A3U devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable multilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); seven flexible, 16-bit timer/counters with compare and PWM channels; seven USARTs; two two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; three serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-channel, 12-bit ADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip debug and programming. The XMEGA A3U devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. 8386B–AVR–12/11 4
XMEGA A3U 3.1 Block Diagram All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. Figure 3-1. XMEGA A3U block diagram. Digital function Analog function Programming, debug, test Oscillator/Crystal/Clock General Purpose I/O XTAL1 XTAL2 PR[0..1] PORT R (2) Oscillator Circuits/ Clock Generation Real Time Counter Watchdog Oscillator DATA BUS Watchdog Timer PA[0..7] PORT A (8) ACA ADCA Event System Controller DMA Controller SRAM Oscillator Control Sleep Controller Power Supervision POR/BOD & RESET VCC GND AREFA BUS Matrix Prog/Debug Controller PDI RESET/ PDI_CLK PDI_DATA Int. Refs. Tempref AES OCD JTAG PORT B AREFB DES ADCB CRC CPU Interrupt Controller PB[0..7]/ JTAG ACB PORT B (8) DACB NVM Controller Flash EEPROM USARTF0 TCF0 PORT F (8) PF[0..7] IRCOM DATA BUS EVENT ROUTING NETWORK TCC0:1 USARTC0:1 SPIC TWIC TCD0:1 USARTD0:1 SPID USB TCE0:1 USARTE0:1 SPIE TWIE To Clock Generator PORT C (8) PORT D (8) PORT E (8) TOSC1 PC[0..7] PD[0..7] PE[0..7] TOSC2 5 8386B–AVR–12/11
Page 1 and 2: Features • High-performance, low-
Page 3: XMEGA A3U 2. Pinout/Block Diagram F
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29 and 30: XMEGA A3U Table 14-1. Reset and int
Page 31 and 32: XMEGA A3U 15.3 Output Driver All po
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39 and 40: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 41 and 42: XMEGA A3U the configuration of thes
Page 43 and 44: XMEGA A3U It is possible to disable
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51 and 52: XMEGA A3U Both internal and externa
Page 53 and 54: XMEGA A3U The DAC has high drive st
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XMEGA A3U Figure 30-1. Analog compa
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XMEGA A3U 32. Pinout and Pin Functi
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XMEGA A3U 32.2 Alternate Pin Functi
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XMEGA A3U Table 32-6. Port F - alte
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XMEGA A3U Base address Name Descrip
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XMEGA A3U Mnemonics Operands Descri
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XMEGA A3U Mnemonics Operands Descri
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XMEGA A3U 35.2 64M2 D Marked Pin# 1
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XMEGA A3U Table 36-3. Operating vol
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XMEGA A3U Table 36-5. Current consu
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XMEGA A3U 36.5 I/O Pin Characterist
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XMEGA A3U Table 36-10. Accuracy cha
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XMEGA A3U Table 36-14. Gain error A
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XMEGA A3U 36.13 Flash and EEPROM Me
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XMEGA A3U 36.14.6 External clock ch
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XMEGA A3U 36.14.7 External 16MHz cr
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XMEGA A3U 36.14.8 External 32.768kH
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XMEGA A3U Table 36-31. SPI timing c
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XMEGA A3U Table 36-32. t HD;STA t L
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XMEGA A3U Figure 37-3. Active mode
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XMEGA A3U Figure 37-7. Active mode
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XMEGA A3U Figure 37-11. Idle mode s
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XMEGA A3U 37.1.3 Power-down mode su
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XMEGA A3U Figure 37-19. Standby sup
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XMEGA A3U 37.2.2 Output Voltage vs.
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XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
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XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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