xmega a3u - Elfa

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XMEGA A3U 22. TWI – Two-Wire Interface 22.1 Features • Two Identical two-wire interface peripherals • Bidirectional, two-wire communication interface – Phillips I 2 C compatible – System Management Bus (SMBus) compatible • Bus master and slave operation supported – Slave operation – Single bus master operation – Bus master in multi-master bus environment – Multi-master arbitration • Flexible slave address match functions – 7-bit and general call address recognition in hardware – 10-bit addressing supported – Address mask register for dual address match or address range masking – Optional software address recognition for unlimited number of addresses • Slave can operate in all sleep modes, including power-down • Slave address match can wake device from all sleep modes • 100kHz and 400kHz bus frequency support • Slew-rate limited output drivers • Input filter for bus noise and spike suppression • Support arbitration between start/repeated start and data bit (SMBus) • Slave arbitration allows support for address resolve protocol (ARP) (SMBus) 22.2 Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I 2 C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. 8386B–AVR–12/11 42
XMEGA A3U It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V CC voltage than used by the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE. 8386B–AVR–12/11 43
Page 1 and 2: Features • High-performance, low-
Page 3 and 4: XMEGA A3U 2. Pinout/Block Diagram F
Page 5 and 6: XMEGA A3U 3.1 Block Diagram All Atm
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29 and 30: XMEGA A3U Table 14-1. Reset and int
Page 31 and 32: XMEGA A3U 15.3 Output Driver All po
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39 and 40: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 41: XMEGA A3U the configuration of thes
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51 and 52: XMEGA A3U Both internal and externa
Page 53 and 54: XMEGA A3U The DAC has high drive st
Page 55 and 56: XMEGA A3U Figure 30-1. Analog compa
Page 57 and 58: XMEGA A3U 32. Pinout and Pin Functi
Page 59 and 60: XMEGA A3U 32.2 Alternate Pin Functi
Page 61 and 62: XMEGA A3U Table 32-6. Port F - alte
Page 63 and 64: XMEGA A3U Base address Name Descrip
Page 65 and 66: XMEGA A3U Mnemonics Operands Descri
Page 67 and 68: XMEGA A3U Mnemonics Operands Descri
Page 69 and 70: XMEGA A3U 35.2 64M2 D Marked Pin# 1
Page 71 and 72: XMEGA A3U Table 36-3. Operating vol
Page 73 and 74: XMEGA A3U Table 36-5. Current consu
Page 75 and 76: XMEGA A3U 36.5 I/O Pin Characterist
Page 77 and 78: XMEGA A3U Table 36-10. Accuracy cha
Page 79 and 80: XMEGA A3U Table 36-14. Gain error A
Page 81 and 82: XMEGA A3U 36.13 Flash and EEPROM Me
Page 83 and 84: XMEGA A3U 36.14.6 External clock ch
Page 85 and 86: XMEGA A3U 36.14.7 External 16MHz cr
Page 87 and 88: XMEGA A3U 36.14.8 External 32.768kH
Page 89 and 90: XMEGA A3U Table 36-31. SPI timing c
Page 91 and 92: XMEGA A3U Table 36-32. t HD;STA t L
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XMEGA A3U Figure 37-3. Active mode
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XMEGA A3U Figure 37-7. Active mode
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XMEGA A3U Figure 37-11. Idle mode s
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XMEGA A3U 37.1.3 Power-down mode su
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XMEGA A3U Figure 37-19. Standby sup
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XMEGA A3U 37.2.2 Output Voltage vs.
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XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
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XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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