xmega a3u - Elfa

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XMEGA A3U 21. USB – Universal Serial Bus Interface 21.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints – One input endpoint per endpoint address – One output endpoint per endpoint address • Endpoint address transfer type selectable to – Control transfers – Interrupt transfers – Bulk transfers – Isochronous transfers • Configurable data payload size per endpoint, up to 1023 bytes • Endpoint configuration and data buffers located in internal SRAM – Configurable location for endpoint configuration data – Configurable location for each endpoint's data buffer • Built-in direct memory access (DMA) to internal SRAM for: – Endpoint configurations – Reading and writing endpoint data • Ping-pong operation for higher throughput and double buffered operation – Input and output endpoint data buffers used in a single direction – CPU/DMA controller can update data buffer during transfer • Multipacket transfer for reduced interrupt load and software intervention – Data payload exceeding maximum packet size is transferred in one continuous transfer – No interrupts or software interaction on packet transaction level • Transaction complete FIFO for workflow management when using multiple endpoints – Tracks all completed transactions in a first-come, first-served work queue • Clock selection independent of system clock source and selection • Minimum 1.5MHz CPU clock required for low speed USB operation • Minimum 12MHz CPU clock required for full speed operation • Connection to event system • On chip debug possibilities during USB transactions 21.2 Overview The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface. The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports data payloads up to 1023 bytes. No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of endpoints in use and 8386B–AVR–12/11 40
XMEGA A3U the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication. Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB. Notation of this is USB. 8386B–AVR–12/11 41
Page 1 and 2: Features • High-performance, low-
Page 3 and 4: XMEGA A3U 2. Pinout/Block Diagram F
Page 5 and 6: XMEGA A3U 3.1 Block Diagram All Atm
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29 and 30: XMEGA A3U Table 14-1. Reset and int
Page 31 and 32: XMEGA A3U 15.3 Output Driver All po
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 43 and 44: XMEGA A3U It is possible to disable
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51 and 52: XMEGA A3U Both internal and externa
Page 53 and 54: XMEGA A3U The DAC has high drive st
Page 55 and 56: XMEGA A3U Figure 30-1. Analog compa
Page 57 and 58: XMEGA A3U 32. Pinout and Pin Functi
Page 59 and 60: XMEGA A3U 32.2 Alternate Pin Functi
Page 61 and 62: XMEGA A3U Table 32-6. Port F - alte
Page 63 and 64: XMEGA A3U Base address Name Descrip
Page 65 and 66: XMEGA A3U Mnemonics Operands Descri
Page 67 and 68: XMEGA A3U Mnemonics Operands Descri
Page 69 and 70: XMEGA A3U 35.2 64M2 D Marked Pin# 1
Page 71 and 72: XMEGA A3U Table 36-3. Operating vol
Page 73 and 74: XMEGA A3U Table 36-5. Current consu
Page 75 and 76: XMEGA A3U 36.5 I/O Pin Characterist
Page 77 and 78: XMEGA A3U Table 36-10. Accuracy cha
Page 79 and 80: XMEGA A3U Table 36-14. Gain error A
Page 81 and 82: XMEGA A3U 36.13 Flash and EEPROM Me
Page 83 and 84: XMEGA A3U 36.14.6 External clock ch
Page 85 and 86: XMEGA A3U 36.14.7 External 16MHz cr
Page 87 and 88: XMEGA A3U 36.14.8 External 32.768kH
Page 89 and 90: XMEGA A3U Table 36-31. SPI timing c
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XMEGA A3U Table 36-32. t HD;STA t L
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XMEGA A3U Figure 37-3. Active mode
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XMEGA A3U Figure 37-7. Active mode
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XMEGA A3U Figure 37-11. Idle mode s
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XMEGA A3U 37.1.3 Power-down mode su
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XMEGA A3U Figure 37-19. Standby sup
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XMEGA A3U 37.2.2 Output Voltage vs.
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XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
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XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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