xmega a3u - Elfa

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XMEGA A3U 15. I/O Ports 15.1 Features • 50 general purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND –Wired-OR – Bus-keeper – Inverted I/O • Input with synchronous and/or asynchronous sensing with interrupts and events – Sense both edges – Sense rising edges – Sense falling edges – Sense low level • Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations • Optional slew rate control • Asynchronous pin change sensing that can wake the device from all sleep modes • Two port interrupts with pin masking per I/O port • Efficient and safe access to port pins – Hardware read-modify-write through dedicated toggle/clear/set registers – Configuration of multiple pins in a single operation – Mapping of port registers into bit-accessible I/O memory space • Peripheral clocks output on port pin • Real-time counter clock output to port pin • Event channels can be output on port pin • Remapping of digital peripheral pin functions – Selectable USART, SPI, and timer/counter input/output pin locations 15.2 Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF and PORTR. 8386B–AVR–12/11 30
XMEGA A3U 15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 8386B–AVR–12/11 31
Page 1 and 2: Features • High-performance, low-
Page 3 and 4: XMEGA A3U 2. Pinout/Block Diagram F
Page 5 and 6: XMEGA A3U 3.1 Block Diagram All Atm
Page 7 and 8: XMEGA A3U 6. AVR CPU 6.1 Features
Page 9 and 10: XMEGA A3U 6.4.1 Hardware Multiplier
Page 11 and 12: XMEGA A3U 7. Memories 7.1 Features
Page 13 and 14: XMEGA A3U 7.3.4 Production Signatur
Page 15 and 16: XMEGA A3U The I/O memory address fo
Page 17 and 18: XMEGA A3U 8. DMAC - Direct Memory A
Page 19 and 20: XMEGA A3U Figure 9-1. Event system
Page 21 and 22: XMEGA A3U Figure 10-1. The clock sy
Page 23 and 24: XMEGA A3U 11. Power Management and
Page 25 and 26: XMEGA A3U 12. System Control and Re
Page 27 and 28: XMEGA A3U 13. WDT - Watchdog Timer
Page 29: XMEGA A3U Table 14-1. Reset and int
Page 33 and 34: XMEGA A3U 15.4 Input sensing Input
Page 35 and 36: XMEGA A3U A timer/counter can be cl
Page 37 and 38: XMEGA A3U 18. AWeX - Advanced Wavef
Page 39 and 40: XMEGA A3U 20. RTC - 16-bit Real-Tim
Page 41 and 42: XMEGA A3U the configuration of thes
Page 43 and 44: XMEGA A3U It is possible to disable
Page 45 and 46: XMEGA A3U 24. USART 24.1 Features
Page 47 and 48: XMEGA A3U 25. IRCOM - IR Communicat
Page 49 and 50: XMEGA A3U 27. CRC - Cyclic Redundan
Page 51 and 52: XMEGA A3U Both internal and externa
Page 53 and 54: XMEGA A3U The DAC has high drive st
Page 55 and 56: XMEGA A3U Figure 30-1. Analog compa
Page 57 and 58: XMEGA A3U 32. Pinout and Pin Functi
Page 59 and 60: XMEGA A3U 32.2 Alternate Pin Functi
Page 61 and 62: XMEGA A3U Table 32-6. Port F - alte
Page 63 and 64: XMEGA A3U Base address Name Descrip
Page 65 and 66: XMEGA A3U Mnemonics Operands Descri
Page 67 and 68: XMEGA A3U Mnemonics Operands Descri
Page 69 and 70: XMEGA A3U 35.2 64M2 D Marked Pin# 1
Page 71 and 72: XMEGA A3U Table 36-3. Operating vol
Page 73 and 74: XMEGA A3U Table 36-5. Current consu
Page 75 and 76: XMEGA A3U 36.5 I/O Pin Characterist
Page 77 and 78: XMEGA A3U Table 36-10. Accuracy cha
Page 79 and 80: XMEGA A3U Table 36-14. Gain error A
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XMEGA A3U 36.13 Flash and EEPROM Me
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XMEGA A3U 36.14.6 External clock ch
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XMEGA A3U 36.14.7 External 16MHz cr
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XMEGA A3U 36.14.8 External 32.768kH
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XMEGA A3U Table 36-31. SPI timing c
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XMEGA A3U Table 36-32. t HD;STA t L
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XMEGA A3U Figure 37-3. Active mode
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XMEGA A3U Figure 37-7. Active mode
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XMEGA A3U Figure 37-11. Idle mode s
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XMEGA A3U 37.1.3 Power-down mode su
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XMEGA A3U Figure 37-19. Standby sup
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XMEGA A3U 37.2.2 Output Voltage vs.
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XMEGA A3U Figure 37-27. I/O pin out
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XMEGA A3U 37.2.3 Thresholds and Hys
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XMEGA A3U 37.3 ADC Characteristics
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XMEGA A3U Figure 37-39. DNL error v
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XMEGA A3U Figure 37-43. Offset erro
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XMEGA A3U Figure 37-47. Noise vs. V
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XMEGA A3U 37.5 Analog Comparator Ch
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XMEGA A3U Figure 37-55. Analog comp
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XMEGA A3U 37.7 BOD Characteristics
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XMEGA A3U Figure 37-63. Reset pin p
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XMEGA A3U 37.9 Power-on Reset Chara
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XMEGA A3U Figure 37-70. 32.768kHz i
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XMEGA A3U 37.10.4 32MHz Internal Os
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XMEGA A3U 37.10.5 32MHz internal os
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XMEGA A3U Figure 37-82. SDA hold ti
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XMEGA A3U 39. Datasheet Revision Hi
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8.1 Features ......................
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27.1 Features .....................
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Atmel Corporation 2325 Orchard Park
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